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this document contains information on a pr oduct under development at spansion, llc. the information is intended to help you eva luate this product. do not design in this product without contacting the factory. spansion reserves th e right to change or discontinue work on this proposed product without notice. publication number s71pl129jxx_00 revision a amendment 5 issue date december 23, 2004 advance information s71pl129jc0/s71pl129jb0/s71pl129ja0 stacked multi-chip produc t (mcp) flash memory and psram 128 megabit (8m x 16-bit) cmos 3.0 volt-only simultaneous operation, page mode flash memory with 64/32/16 megabit (4m/2m/1m x 16-bit) pseudo-static ram distinctive characteristics mcp features ? power supply voltage of 2.7 to 3.1 volt ? high performance ? 65ns (65ns flash, 70ns psram) ? package ? 8 x 11.6 x 1.2 mm 64 ball fbga ? operating temperature ? ?25c to +85c (wireless) ? ?40c to +85c (industrial) ? dual ce# flash memory general description the s71pl129j series is a product line of stacked multi-chip product (mcp) pack- ages and consists of: ? one s29pl129j flash memory die ? one 16m, 32m, or 64m psram the products covered by this document ar e listed in the table below. for details about their specifications, please refer to the individual consti tuent datasheets for further details. flash memory density 128mb psram density 64mb s71pl129jc0 32mb s71pl129jb0 16mb s71pl129ja0
2 s71pl129jc0/s71pl129jb0/s71pl129ja0 s71pl129jxx_00_a5_e december 23, 2004 advance information product selector guide 128 mb flash memory device-model# psram density flash access time (ns) (p)sram access time (ns) psram type package s71pl129ja0-9p 16m psram 65 70 type 7 tla064 s71pl129jb0-9z 32m psram 65 70 type 7 tla064 s71pl129jb0-9b 32m psram 65 70 type 2 tla064 s71pl129jb0-9u 32m psram 65 70 type 6 tla064 s71pl129jc0-9z 64m psram 65 70 type 7 tla064 s71pl129jc0-9u 64m psram 65 70 type 6 tla064
december 23, 2004 s71pl129jxx_00_a5 3 advance information s71pl129jc0/s71pl129jb0/s71pl129ja0 distinctive characteristics . . . . . . . . . . . . . . . . . . . 1 mcp features ........................................................................................................ 1 general description . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . .2 128 mb flash memory ..........................................................................................2 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . .6 connection diagram . . . . . . . . . . . . . . . . . . . . . . . .7 input/output description . . . . . . . . . . . . . . . . . . . 8 pin description ......................................................................................................8 logic symbol ...........................................................................................................8 ordering information . . . . . . . . . . . . . . . . . . . . . . . .9 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . 11 tla064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package ............................................................................................ 11 s29pl129j for mcp general description . . . . . . . . . . . . . . . . . . . . . . . . 14 simultaneous read/write operation with zero latency ...................... 14 page mode features ........................................................................................... 14 standard flash memory features ..... .............................................................. 14 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 device bus operations . . . . . . . . . . . . . . . . . . . . . . 19 table 1. pl129j device bus operations ................................ 19 requirements for reading array data ......................................................... 19 random read (non-page read) ...... ......................................................... 20 page mode read ............................................................................................. 20 table 2. page select .......................................................... 20 simultaneous read/write operation .......................................................... 20 writing commands/command sequences ................................................. 21 accelerated program operation ..... .......................................................... 21 autoselect functions ....................... .............................................................. 21 standby mode ........................................................................................................21 automatic sleep mode ..................................................................................... 22 reset#: hardware reset pin ........... ............................................................. 22 output disable mode ....................................................................................... 22 table 3. s29pl129j sector architecture ............................... 23 table 4. secured silicon sector addresses ............................ 29 autoselect mode ................................................................................................ 29 table 5. autoselect codes for pl129j ................................... 30 table 6. pl129j boot sector/secto r block addresses for protection/ unprotection ..................................................................... 31 selecting a sector prot ection mode ..............................................................32 table 7. sector protection schemes ..................................... 32 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . 32 persistent sector protection ......... ..................................................................32 password sector protection .............. ..............................................................32 wp# hardware protection .............................................................................32 selecting a sector prot ection mode ..............................................................32 persistent sector protection . . . . . . . . . . . . . . . . 33 persistent protection bit (ppb) .......................................................................33 persistent protection bit lock (ppb lock) .................................................33 dynamic protection bit (dyb) .......................................................................33 persistent sector protec tion mode locking bit ........................................35 password protection mode . . . . . . . . . . . . . . . . . 35 password and password mode lockin g bit ................................................36 64-bit password ...................................................................................................36 write protect (wp#) ....................................................................................... 36 persistent protection bit lock . .................................................................. 37 high voltage sector protection ... .................................................................. 37 figure 1. in-system sector protection/sector unprotection algorithms........................................................................ 38 temporary sector unprotect .......... .............................................................. 39 figure 2. temporary sector unprotect operation ................... 39 secured silicon sector flash memor y region ........................................... 39 factory-locked area (64 words) ..............................................................40 customer-lockable area (64 words) ......................................................40 secured silicon sector protection bits ....................................................40 figure 3. secured silicon sector protect verify ...................... 41 hardware data protection ............... ............................................................... 41 low vcc write inhibit ................................................................................. 41 write pulse ?glitch? protection ................................................................ 41 logical inhibit .................................................................................................... 41 power-up write inhibit ................................................................................ 41 common flash memory interface (cfi) . . . . . . 42 table 8. cfi query identification string ................................ 42 table 9. system interface string ......................................... 43 table 10. device geometry definition ................................... 43 table 11. primary vendor-specific extended query ................ 43 command definitions . . . . . . . . . . . . . . . . . . . . . . 45 reading array data ............................. .............................................................. 45 reset command ................................................................................................. 45 autoselect command sequence .......... ..........................................................46 enter secured silicon sector/exit se cured silicon sect or command se- quence ....................................................................................................................46 word program command sequence . .......................................................... 46 unlock bypass command sequence .. ...................................................... 47 figure 4. program operation ............................................... 48 chip erase command sequence ...................................................................48 sector erase command sequence ................................................................49 figure 5. erase operation ................................................... 50 erase suspend/erase resume comma nds ..................................................50 password program command ........................................................................ 51 password verify command .............................................................................. 51 password protection mode locking bit program command ............... 51 persistent sector protection mo de locking bit program command 52 secured silicon sector protection bit program command .................. 52 ppb lock bit set command ............................................................................ 52 dyb write command ...................................................................................... 52 password unlock command ................ .......................................................... 52 ppb program command .................................................................................. 53 all ppb erase command .................................................................................. 53 dyb write command ...................................................................................... 53 ppb lock bit set command ............................................................................ 53 command ............................................................................................................. 54 command definitions tables ......................................................................... 54 table 12. memory array command definitions ...................... 54 table 13. sector protection command definitions .................. 55 write operation status . . . . . . . . . . . . . . . . . . . . 56 dq7: data# polling ............................................................................................ 56 figure 6. data# polling algorithm ........................................ 58 ry/by#: ready/busy# ....................................................................................... 58 dq6: toggle bit i ...............................................................................................58 figure 7. toggle bit algorithm ............................................. 59 dq2: toggle bit ii ..............................................................................................60 reading toggle bits dq6/dq2 .....................................................................60 dq5: exceeded timing limits ........................................................................60 dq3: sector erase time r ................................................................................. 61
4 s71pl129jxx_00_a5 december 23, 2004 advance information table 14. write operation status ......................................... 61 absolute maximum ratings . . . . . . . . . . . . . . . . . .62 figure 8. maximum overshoot waveforms............................. 62 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 63 industrial (i) devices ..........................................................................................63 extended (e) devices .... .....................................................................................63 supply voltages ....................................................................................................63 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . .64 table 15. cmos compatible ................................................ 64 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . .65 test conditions ...................................................................................................65 figure 9. test setups......................................................... 65 table 16. test specifications ............................................... 65 switching waveforms ........................................................................................65 table 17. key to switching waveforms ................................. 65 figure 10. input waveforms and measurement levels............. 66 vcc ramprate .................................................................................................. 66 read operations ................................................................................................ 66 table 18. read-only operations .......................................... 66 figure 11. read operation timings ....................................... 67 figure 12. page read operation timings ............................... 67 reset ...................................................................................................................... 68 table 19. hardware reset (reset#) .................................... 68 figure 13. reset timings..................................................... 68 erase/program operations ............................................................................. 69 table 20. erase and program operations .............................. 69 timing diagrams ................................................................................................. 70 figure 14. program operation timings .................................. 70 figure 15. accelerated program timing diagram .................... 70 figure 16. chip/sector erase operation timings ..................... 71 figure 17. back-to-back read/write cycle timings ................. 72 figure 18. data# polling timings (during embedded algorithms) ............................................ 72 figure 19. toggle bit timings (during embedded algorithms) .. 73 figure 20. dq2 vs. dq6 ...................................................... 73 protect/unprotect . . . . . . . . . . . . . . . . . . . . . . . . 74 table 21. temporary sector unprotect ................................. 74 figure 21. temporary sector unprotect timing diagram.......... 74 figure 22. sector/sector block protect and unprotect timing diagram............................................................................ 75 controlled erase operations ..........................................................................76 table 22. alternate ce# controlled erase and program operations ........................................................... 76 table 23. alternate ce# controlled write (erase/program) operation timings ............................................................. 77 table 24. ce1#/ce2# timing ............................................. 77 figure 23. timing diagram for alternating between ce1# and ce2# control ............................................................................. 78 table 25. erase and programming performance .................... 78 bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . 78 psram type 6 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 functional description . . . . . . . . . . . . . . . . . . . . . 80 absolute maximum ratings . . . . . . . . . . . . . . . . . 80 ac characteristics and operating conditions . 81 ac test conditions . . . . . . . . . . . . . . . . . . . . . . . 82 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . .83 read timings ........................................................................................................83 figure 24. read cycle ......................................................... 83 figure 25. page read cycle (8 words access) ........................ 84 write timings ...................................................................................................... 85 figure 26. write cycle #1 (we# controlled) (see note 8)....... 85 figure 27. write cycle #2 (ce# controlled) (see note 8) ....... 86 deep power-down timing ..............................................................................86 figure 28. deep power down timing .................................... 86 power-on timing ................................................................................................86 figure 29. power-on timing ................................................ 86 provisions of address skew ............................................................................87 read ....................................................................................................................87 figure 30. read................................................................. 87 write .................................................................................................................. 87 figure 31. write ................................................................ 87 psram type 1 functional description . . . . . . . . . . . . . . . . . . . . . 88 absolute maximum ratings . . . . . . . . . . . . . . . . 88 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 89 timing test conditions . . . . . . . . . . . . . . . . . . . . 94 output load circuit .......................................................................................... 95 figure 32. output load circuit............................................. 95 power up sequence . . . . . . . . . . . . . . . . . . . . . . . 95 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 96 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 107 read cycle ...........................................................................................................107 figure 33. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih ) .............................. 107 figure 34. timing waveform of read cycle (we# = zz# = v ih )......................................................... 108 figure 35. timing waveform of page mode read cycle (we# = zz# = v ih )......................................................... 109 write cycle ..........................................................................................................110 figure 36. timing waveform of write cycle (we# control, zz# = v ih )................................................ 110 figure 37. timing waveform of write cycle (ce# control, zz# = v ih )................................................. 110 figure 38. timing waveform of page mode write cycle (zz# = v ih ) ................................................................... 111 partial array self refresh (par) .....................................................................111 temperature compensated refresh (f or 64mb) .....................................112 deep sleep mode ...............................................................................................112 reduced memory size (for 32m and 16m) ..................................................112 other mode register settings (for 64m) ....................................................112 figure 39. mode register .................................................. 113 figure 40. mode register upda te timings (ub#, lb#, oe# are don?t care)..................................................................... 113 figure 41. deep sleep mode - en try/exit timings (for 64m)... 114 figure 42. deep sleep mo de - entry/exit timings (for 32m and 16m)........................................................... 114 type 2 psram features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 product information . . . . . . . . . . . . . . . . . . . . . . 118 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 power up sequence . . . . . . . . . . . . . . . . . . . . . . . 119 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 119 power up ..............................................................................................................119 figure 43. power up 1 (cs1# controlled) ........................... 119 figure 44. power up 2 (cs2 controlled).............................. 119 functional description . . . . . . . . . . . . . . . . . . . . 120 absolute maximum ratings . . . . . . . . . . . . . . . 120 dc recommended operating conditions . . . . 120
december 23, 2004 s71pl129jxx_00_a5 5 advance information dc and operating characteristics . . . . . . . . . . . 121 common ............................................................................................................... 121 16m psram ......................................................................................................... 122 32m psram ........................................................................................................ 122 64m psram ........................................................................................................ 123 128m psram ....................................................................................................... 123 ac operating conditions . . . . . . . . . . . . . . . . . 124 test conditions (test load and test input/output reference) ....... 124 figure 45. output load ..................................................... 124 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 126 read timings ...................................................................................................... 126 figure 46. timing waveform of read cycle(1)...................... 126 figure 47. timing waveform of read cycle(2)...................... 126 figure 48. timing waveform of page cycle (page mode only) 127 write timings .................................................................................................... 127 figure 49. write cycle #1 (we# controlled) ........................ 127 figure 50. write cycle #2 (cs1# controlled) ....................... 128 figure 51. timing waveform of write cycle(3) (cs2 controlled) .............................................................. 128 figure 52. timing waveform of write cycle(4) (ub#, lb# controlled) ...................................................................... 129 psram type 7 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . 130 functional description . . . . . . . . . . . . . . . . . . . . . 131 power down (for 32m, 64m only) . . . . . . . . . . . . 131 power down ....................................................................................................... 131 power down program sequence ................................................................. 132 address key ....................................................................................................... 132 absolute maximum ratings . . . . . . . . . . . . . . . . . 133 package capacitance . . . . . . . . . . . . . . . . . . . . . . 133 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 134 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 135 read operation ..................................................................................................135 write operation ............................................................................................... 136 power down parameters ...................... ......................................................... 137 other timing parameters ............................................................................... 137 ac test conditions .........................................................................................138 ac measurement output load circuits ...................................................138 figure 53. ac output load circuit ? 16 mb.......................... 138 figure 54. ac output load circuit ? 32 mb and 64 mb .......... 138 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139 read timings .......................................................................................................139 figure 55. read timing #1 (basic timing) .......................... 139 figure 56. read timing #2 (oe# address access................. 139 figure 57. read timing #3 (lb#/ub# byte access) ............. 140 figure 58. read timing #4 (p age address access after ce1# control access for 32m and 64m only) ............................... 140 figure 59. read timing #5 (ran dom and page address access for 32m and 64m only) ......................................................... 141 write timings ......................................................................................................141 figure 60. write timing #1 (basic timing) .......................... 141 figure 61. write timing #2 (we# control).......................... 142 figure 62. write timing #3-1 (we#/lb#/ub# byte write control) .................................. 142 figure 63. write timing #3-3 (we#/lb#/ub# byte write control) .................................. 143 figure 64. write timing #3-4 (we#/lb#/ub# byte write control) .................................. 143 read/write timings ..........................................................................................144 figure 65. read/write timing #1-1 (ce1# control) ............. 144 figure 66. read / write timing #1-2 (ce1#/we#/oe# control) ................................................ 144 figure 67. read / write timing #2 (oe#, we# control) ....... 145 figure 68. read / write timing #3 (oe#, we#, lb#, ub# control) ........................................ 145 figure 69. power-up timing #1 ......................................... 146 figure 70. power-up timing #2 ......................................... 146 figure 71. power down entry and exit timing ..................... 146 figure 72. standby entry timing after read or write ............ 147 figure 73. power down program timing (for 32m/64m only) . 147 revision summary
6 s71pl129jxx_00_a5 december 23, 2004 advance information mcp block diagram v ss reset# flash 1 io 15 -io 0 v cc f dq 15 to dq 0 ry/by# wp#/acc v cc v cc ce2#f flash-only address shared address oe# we# v ccs v cc ce#s ub#s lb#s ce# ub# lb# psram ce2#ps ce1#f cem1#ps
december 23, 2004 s71pl129jxx_00_a5 7 advance information connection diagram note: may be shared depending on density: ? a21 is shared for the 64m psram configuration. ? a20 is shred for the 32m psram configuration. ? a19 is shared for the 16m psram configuration. note: it is advised to tie j5 an d l5 together on the board. mcp flash-only addresses shared addresses s71pl129jc0 a22 a21-a0 s71pl129jb0 a22-a21 a20-a0 s71pl129ja0 a22-a20 a19-a0 e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 k4 dq10 dq2 d4 e6 ce2s a20 j6 dq4 k6 vccs rfu d6 rfu e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 k7 dq12 dq5 d7 e5 rst#f ry/by# j5 dq3 k5 vccf dq11 d5 rfu e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 k8 dq7 dq14 d8 e9 f9 a21 g9 ce2# h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# k3 dq0 ce1#s dq8 d3 e2 f2 a2 g2 a1 h2 a0 j2 ce1#f h6 h5 b6 b5 ram only shared (note 1) flash only legend reserved fo r future use rfu rfu l6 l5 lb# c4 we# c6 a8 c7 wp/acc c5 a11 c8 a7 c3 a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc 64-ball fine-pitch ball grid array (top view, balls facing down)
8 s71pl129jxx_00_a5 december 23, 2004 advance information input/output description pin description a21?a0 = 22 address inputs (common) dq15?dq0 = 16 data inputs/outputs (common) ce1#f = chip enable 1 (flash) ce2#f = chip enable 2 (flash) ce1#ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub# = upper byte control (psram) lb# = lower byte control (psram) reset# = hardware reset pin, active low (flash 1) wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc ps = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce1#f oe# we # reset# r y/by# wp#/acc ub# ce2#f ce2ps ce1#ps lb#
december 23, 2004 s71pl129jxx_00_a5 9 advance information ordering information the order number is formed by a va lid combinations of the following: s71pl 129 j b0 ba w 9 z 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number see valid combinations table. package modifier 9 = 8 x 11.6 mm, 1.2 mm height, 64 balls (tla064) temperature range w=wireless (-25 c to +85 c) i = industrial (-40 c to +85 c) package type ba = fine-pitch bga lead (pb)-free compliant package bf = fine-pitch bga lead (pb)-free package psram density c0 = 64 mb psram b0 = 32 mb psram a0 = 16 mb psram process technology j = 110 nm, floating gate technology flash density 129 = 128mb, dual ce# product family s71pl multi-chip product (mcp) 3.0-volt simultaneous read/write, page mode flash memory and ram
10 s71pl129jxx_00_a5 december 23, 2004 advance information s71pl129j valid combinations speed options (ns) (p)sram type/access time (ns) package marking base ordering part number package & temperature package modifier/ model number packing type s71pl129ja0 baw 9p 0, 2, 3 ( note 1 )65 psram 7 / 70 ( note 2 ) s71pl129jb0 9z psram 7 / 70 s71pl129jb0 9b psram 2 / 70 s71pl129jb0 9u psram 6 / 70 s71pl129jc0 9z psram 7 / 70 s71pl129jc0 9u psram 6 / 70 s71pl129ja0 bfw 9p 0, 2, 3 ( note 1 )65 psram 7 / 70 s71pl129jb0 9z psram 7 / 70 s71pl129jb0 9b psram 2 / 70 s71pl129jb0 9u psram 6 / 70 s71pl129jc0 9z psram 7 / 70 s71pl129jc0 9u psram 6 / 70 s71pl129ja0 bai 9p 0, 2, 3 ( note 1 )65 psram 7 / 70 s71pl129jb0 9z psram 7 / 70 s71pl129jb0 9b psram 2 / 70 s71pl129jb0 9u psram 6 / 70 s71pl129jc0 9z psram 7 / 70 s71pl129jc0 9u psram 6 / 70 s71pl129ja0 bfi 9p 0, 2, 3 ( note 1 )65 psram 7 / 70 s71pl129jb0 9z psram 7 / 70 s71pl129jb0 9b psram 2 / 70 s71pl129jb0 9u psram 6 / 70 s71pl129jc0 9z psram 7 / 70 s71pl129jc0 9u psram 6 / 70 notes: 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. 3. contact factory for availability of any of the above opns. ram type availability ma y vary over time. valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult your local sales office to confirm avail- ability of specific valid combinations and to check on newly released combinations.
december 23, 2004 s71pl129jxx_00_a5 11 advance information physical dimensions tla064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3352 \ 16-038.22a package tla 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10, f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.20 c 0.08 c b 64x 6 0.08 m c 0.15 m c a b a2 a a1 side view l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7 10 index mark c 0.15 (2x) (2x) c 0.15 b a d e pin a1 top view corner
publication number s29pl129j_mcp_00 revision a amendment 0 issue date june 4, 2004 advance information s29pl129j for mcp 128 megabit (8 m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory with enhanced versatileio tm control distinctive characteristics architectural advantages ? 128 mbit page mode devices ? page size of 8 words: fast page read access from random locations within the page ? single power supply operation ? full voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications ? dual chip enable inputs (only in pl129j) ? two ce# inputs control sele ction of each half of the memory space ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations ? flexbank architecture ? 4 separate banks, with up to two simultaneous operations per device ? ce#1 controlled banks: bank 1a: - 16mbit (4kw x 8 and 32kw x 31) bank 1b: - 48mbit (32kw x 96) ? ce#2 controlled banks: bank 2a: - 48 mbit (32kw x 96) bank 2b: - 16mbit (4kw x 8 and 32kw x 31) ? enhanced versatilei/o tm (v io ) control ? output voltage generated and input voltages tolerated on all control inpu ts and i/os is determined by the voltage on the v io pin ? secured silicon sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words ? both top and bottom boot blocks in one device ? manufactured on 110 nm process technology ? data retention: 20 years typical ? cycling endurance: 1 million cycles per sector typical performance characteristics ? high performance ? page access times as fast as 20 ns ? random access times as fast as 55 ns ? power consumption (typical values at 10 mhz) ? 45 ma active read current ? 17 ma program/erase current ? 0.2 a typical standby mode current software features ? software command-set compatible with jedec 42.4 standard ? backward compatible with am29f, am29lv, am29dl, and am29pdl families and mbm29qm/rm, mbm29lv, mbm29dl, mbm29pdl families ? cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ? erase suspend / erase resume ? suspends an erase operation to allow read or program operations in other sectors of same bank ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data ? wp#/ acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 4k word sectors. ?at v ih , allows removal of sector protection ?at v hh , provides accelerated programming in a factory setting ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups datasheet
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 13 advance information to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
14 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information general description the pl129j is a 128 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory device organized as 8 mwords. the word-wide data (x16) appears on dq15-dq0. this device can be pro - grammed in-system or in standard eprom programmers. a 12.0 v v pp is not required for write or erase operations. the device offers fast page access time s of 20 to 30 ns, with corresponding ran - dom access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. note: device pl129j has 2 chip enable inputs (ce1#, ce2#). simultaneous read/write operation with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into 4 bank s, which can be considered to be four separate memory arrays as far as certain operations are concerned. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from wa iting for the completion of a program or erase operation, greatly im proving system performance. the device can be organized in both to p and bottom sector configurations. the banks are organized as follows: page mode features the page size is 8 words. after initial pa ge access is accomplished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.6 v) for both read and write functions. internally ge nerated and regulated voltages are pro - vided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single- power-supply flash standard . commands are written to the command regis - ter using standard microprocessor write timi ng. register contents serve as inputs to an internal state-machin e that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. the unlock bypass mode facilita tes faster programming times by requiring only two bank pl129j sectors ce# control 1a 16 mbit (4 kw x 8 and 32 kw x 31) ce1# 1b 48 mbit (32 kw x 96) ce1# 2a 48 mbit (32 kw x 96) ce2# 2b 16 mbit (4 kw x 8 and 32 kw x 31) ce2#
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 15 advance information write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. the host system can detect whether a prog ram or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the de vice is ready to read array data or ac - cept another command. the sector erase architecture allows me mory sectors to be erased and repro - grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automat - ically inhibits write operations during power transitions. the hardware sector protection feature disables both progra m and erase operations in any combina - tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secured silicon sector area (one time program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when addresses have been stable for a specified amount of ti me, the device enters the automatic sleep mode . the system can also place the device in to the standby mode. power consumption is greatly reduced in both these modes. the device electrically erases all bits wi thin a sector simultaneously via fowler- nordheim tunneling. the data is prog rammed using hot electron injection.
16 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information block diagram notes: 1. ry/by# is an open drain output. 2. for pl129j there are two ce# (ce1# and ce2#) v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# (see note) amax?a3 a2?a0 ce# we# dq15?dq0 v io oe#
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 17 advance information simultaneous read/write block diagram (pl129j) notes: 1. amax = a21 (pl129j) v cc v ss bank 1a address bank 1b address a21?a0 reset# we# ce1# dq0?dq15 ce2# state control & command register ry/by# bank 1a x-decoder oe# dq15?dq0 status control a21?a0 a21?a0 a21?a0 a21?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 1b x-decoder y-gate bank 2a x-decoder bank 2b x-decoder y-gate bank 2a address bank 2b address ce1#=l ce2#=h ce1#=h ce2#=l wp#/acc
18 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information pin description amax?a0 = address bus dq15?dq0 = 16-bit data inputs/outputs/float ce# = chip enable inputs oe# = output enable input we# = write enable v ss = device ground nc = pin not connected internally ry/by# = ready/busy output and open drain. when ry/by#= v ih , the device is ready to accept read operations and commands. when ry/by#= v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. wp#/acc = write protect/acceleration input. when wp#/acc= v il , the highest and lowest two 4k-word sectors are write protected regardless of other sector protection configurations. when wp#/ acc= v ih , these sector are unprotected unless the dyb or ppb is programmed. when wp#/acc= 12v, program and erase operations are accelerated. v io = input/output buffer power supply 2.7 v to 3.6 v v cc =chip power supply (2.7 v to 3.6 v or 2.7 to 3.3 v) reset# = hardware reset pin ce1#, ce2# = chip enable inputs. ce1# controls the 64mb in banks 1a and 1b. ce2# controls the 64 mb in banks 2a and 2b. notes: 1. amax = a21 logic symbol max+1 16 dq15?dq0 amax?a0 ce# oe# we# reset# ry/by# wp#/acc v io (v ccq )
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 19 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable me mory location. the register is a latch used to store the commands, along wi th the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state mach ine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and control levels re - quired, and the resulting output. the foll owing subsections describe each of these operations in further detail. legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 8.5?9.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. the sector protect and sector unprotect functions ma y also be implemented via pr ogramming equipment. see ? ?high voltage sector protection? on page 37 .? 2. wp#/acc must be high when writing to upper two and lower two sectors. requirements for reading array data to read array data from the outputs, the system must drive the oe# and appro - priate ce# pins to v il . in pl129j, ce1# and ce2# are the power control and select the lower (ce1#) or upper (ce2#) halves of the device. ce# is the power control. oe# is the output control and ga tes array data to the output pins. we# should remain at v ih . the internal state machine is set for re ading array data upon device power-up, or after a hardware reset. this ensures th at no spurious alteration of the memory content occurs during the power transiti on. no command is necessary in this mode to obtain array data. standard microprocessor re ad cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. see ta b l e 24 for timing specifications and figure 11 for the timing diagram. i cc1 in the dc characteristics table represen ts the active current specification for reading array data. ta b l e 1 . pl129j device bus operations operation ce1# ce2# oe# we# reset# wp#/acc addresses (a21?a0) dq15? dq0 read l h l h h x a in d out h l write l h h l h x ( note 2 ) a in d in h l standby v io 0.3 v v io 0.3 v x x v io 0.3 v x x high-z output disable l l h h h x x high-z reset x x x x l x x high-z temporary sector unprotect (high voltage) x x x x v id x a in d in
20 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad - dresses and stable ce# to valid data at the output inputs. the output enable access time is the delay from the falling edge of the oe# to valid data at the out - put inputs (assuming the addresses have been stable for at least t acc ?t oe time). page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. address bits amax?a3 select an 8 word page, and address bits a2?a0 select a specific word within that page. this is an asyn - chronous operation with the microprocess or supplying the speci fic word location. the random or initial page access is t acc or t ce and subsequent page read ac - cesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce1# and ce#2 are deasserted (=v ih ), the reassertion of ce1# or ce#2 for su bsequent access has access time of t acc or t ce . here again, ce1#/ce#2 selects the devi ce and oe# is the output control and should be used to gate data to the output inputs if th e device is selected. fast page mode accesses are obtained by ke eping amax?a3 constant and changing a2?a0 to select the specific word within that page. simultaneous read/write operation in addition to the conventi onal features (read, program, erase-suspend read, and erase-suspend program), the device is capa ble of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). the bank can be selected by bank addresses (a21?a19) with zero latency. the simultaneous operation can execute multi-function mode in the same bank. ta b l e 2 . page select word a2 a1 a0 word 0 0 0 0 word 1 0 0 1 word 2 0 1 0 word 3 0 1 1 word 4 1 0 0 word 5 1 0 1 word 6 1 1 0 word 7 1 1 1 bank ce1# ce2# pl129j: a21?a20 bank 1a 0 1 00 bank 1b 0 1 01, 10, 11
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 21 advance information writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of me mory), the system must drive we# and ce1# or ce#2 to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once a bank enters the unlock bypass mo de, only two write cycles are required to program a word, instead of four. ?word program command sequence? on page 46 has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 4 indicates the set of address space th at each sector occupies. a ?bank ad - dress? is the set of address bits required to uniquely select a bank. similarly, a ?sector address? refers to the address bits required to uniquely select a sector. ?command definitions? on page 45 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. i cc2 in the dc characteristics table represen ts the active current specification for the write mode. see the timing specification tables and timing diagrams in ?re - set? for write operations. accelerated program operation the device offers accelerated program op erations through the acc function. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device au tomatically enters the afore - mentioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin re - turns the device to normal operation. note that v hh must not be asserted on wp#/acc for operations other than acce lerated programming, or device damage may result. in addition, the wp#/ acc pin should be raised to v cc when not in use. that is, the wp#/acc pin should not be left floating or unconnected; incon - sistent behavior of the device may result. autoselect functions if the system writes the autoselect co mmand sequence, the device enters the au - toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. see ?secured silicon sector addresses? on page 29 and ?autoselect command sequence? on page 46 for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, curre nt consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. bank 2a 1 0 00, 01, 10 bank 2b 1 0 11
22 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information the device enters the cmos standby mode when the ce1# or ce#2 and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce1# or ce#2 and reset# are held at v ih , but not within v io 0.3 v, the device is in standby mode, but the standby current is greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, be fore it is ready to read data. if the device is deselected during erasure or programming, the device draws ac - tive current until the operation is completed. i cc3 in ?dc characteristics? represents the cmos standby current specification. automatic sleep mode the automatic sleep mode minimizes flas h device energy consumption. the de - vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is indepe ndent of the ce#, we#, and oe# con - trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. note that during automa tic sleep mode, oe# must be at v ih before the device reduces current to the stated sleep mode specification. i cc5 in ?dc characteristics? represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware meth od of resetting the device to reading array data. when the reset# pin is dr iven low for at least a period of t rp , the device immediately terminates any operat ion in progress, tr istates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal st ate machine to reading array data. the op - eration that was interrupted should be reinitiated once the device is ready to accept another command sequence , to ensure data integrity. current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current ( i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current is greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabli ng the system to read the boot-up firm - ware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin re - mains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/ by# to determine whet her the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristics tables for reset# parameters and to figure 13 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins (except for ry/by#) are placed in the highest impedance state
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 23 advance information ta b l e 3 . s29pl129j sector architecture (sheet 1 of 7) bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16) bank 1a sa1-0 0 1 0000000000 4 000000h?000fffh sa1-1 0 1 0000000001 4 001000h?001fffh sa1-2 0 1 0000000010 4 002000h?002fffh sa1-3 0 1 0000000011 4 003000h?003fffh sa1-4 0 1 0000000100 4 004000h?004fffh sa1-5 0 1 0000000101 4 005000h?005fffh sa1-6 0 1 0000000110 4 006000h?006fffh sa1-7 0 1 0000000111 4 007000h?007fffh sa1-8 0 1 0000001xxx 32 008000h?00ffffh sa1-9 0 1 0000010xxx 32 010000h?017fffh sa1-10 0 1 0000011xxx 32 018000h?01ffffh sa1-11 0 1 0000100xxx 32 020000h?027fffh sa1-12 0 1 0000101xxx 32 028000h?02ffffh sa1-13 0 1 0000110xxx 32 030000h?037fffh sa1-14 0 1 0000111xxx 32 038000h?03ffffh sa1-15 0 1 0001000xxx 32 040000h?047fffh sa1-16 0 1 0001001xxx 32 048000h?04ffffh sa1-17 0 1 0001010xxx 32 050000h?057fffh sa1-18 0 1 0001011xxx 32 058000h?05ffffh sa1-19 0 1 0001100xxx 32 060000h?067fffh sa1-20 0 1 0001101xxx 32 068000h?06ffffh sa1-21 0 1 0001110xxx 32 070000h?077fffh sa1-22 0 1 0001111xxx 32 078000h?07ffffh sa1-23 0 1 0010000xxx 32 080000h?087fffh sa1-24 0 1 0010001xxx 32 088000h?08ffffh sa1-25 0 1 0010010xxx 32 090000h?097fffh sa1-26 0 1 0010011xxx 32 098000h?09ffffh sa1-27 0 1 0010100xxx 32 0a0000h?0a7fffh sa1-28 0 1 0010101xxx 32 0a8000h?0affffh sa1-29 0 1 0010110xxx 32 0b0000h?0b7fffh sa1-30 0 1 0010111xxx 32 0b8000h?0bffffh sa1-31 0 1 0011000xxx 32 0c0000h?0c7fffh sa1-32 0 1 0011001xxx 32 0c8000h?0cffffh sa1-33 0 1 0011010xxx 32 0d0000h?0d7fffh sa1-34 0 1 0011011xxx 32 0d8000h?0dffffh sa1-35 0 1 0011100xxx 32 0e0000h?0e7fffh sa1-36 0 1 0011101xxx 32 0e8000h?0effffh sa1-37 0 1 0011110xxx 32 0f0000h?0f7fffh sa1-38 0 1 0011111xxx 32 0f8000h?0fffffh
24 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information bank 1b sa1-39 0 1 0100000xxx 32 100000h?107fffh sa1-40 0 1 0100001xxx 32 108000h?10ffffh sa1-41 0 1 0100010xxx 32 110000h?117fffh sa1-42 0 1 0100011xxx 32 118000h?11ffffh sa1-43 0 1 0100100xxx 32 120000h?127fffh sa1-44 0 1 0100101xxx 32 128000h?12ffffh sa1-45 0 1 0100110xxx 32 130000h?137fffh sa1-46 0 1 0100111xxx 32 138000h?13ffffh sa1-47 0 1 0101000xxx 32 140000h?147fffh sa1-48 0 1 0101001xxx 32 148000h?14ffffh sa1-49 0 1 0101010xxx 32 150000h?157fffh sa1-50 0 1 0101011xxx 32 158000h?15ffffh sa1-51 0 1 0101100xxx 32 160000h?167fffh sa1-52 0 1 0101101xxx 32 168000h?16ffffh sa1-53 0 1 0101110xxx 32 170000h?177fffh sa1-54 0 1 0101111xxx 32 178000h?17ffffh sa1-55 0 1 0110000xxx 32 180000h?187fffh sa1-56 0 1 0110001xxx 32 188000h?18ffffh sa1-57 0 1 0110010xxx 32 190000h?197fffh sa1-58 0 1 0110011xxx 32 198000h?19ffffh sa1-59 0 1 0110100xxx 32 1a0000h?1a7fffh sa1-60 0 1 0110101xxx 32 1a8000h?1affffh sa1-61 0 1 0110110xxx 32 1b0000h?1b7fffh sa1-62 0 1 0110111xxx 32 1b8000h?1bffffh sa1-63 0 1 0111000xxx 32 1c0000h?1c7fffh sa1-64 0 1 0111001xxx 32 1c8000h?1cffffh sa1-65 0 1 0111010xxx 32 1d0000h?1d7fffh sa1-66 0 1 0111011xxx 32 1d8000h?1dffffh sa1-67 0 1 0111100xxx 32 1e0000h?1e7fffh sa1-68 0 1 0111101xxx 32 1e8000h?1effffh sa1-69 0 1 0111110xxx 32 1f0000h?1f7fffh sa1-70 0 1 0111111xxx 32 1f8000h?1fffffh sa1-71 0 1 1000000xxx 32 200000h?207fffh sa1-72 0 1 1000001xxx 32 208000h?20ffffh sa1-73 0 1 1000010xxx 32 210000h?217fffh sa1-74 0 1 1000011xxx 32 218000h?21ffffh sa1-75 0 1 1000100xxx 32 220000h?227fffh sa1-76 0 1 1000101xxx 32 228000h?22ffffh sa1-77 0 1 1000110xxx 32 230000h?237fffh sa1-78 0 1 1000111xxx 32 238000h?23ffffh sa1-79 0 1 1001000xxx 32 240000h?247fffh sa1-80 0 1 1001001xxx 32 248000h?24ffffh sa1-81 0 1 1001010xxx 32 250000h?257fffh sa1-82 0 1 1001011xxx 32 258000h?25ffffh table 3. s29pl129j sector architecture (sheet 2 of 7) bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 25 advance information bank 1b sa1-83 0 1 1001100xxx 32 260000h?267fffh sa1-84 0 1 1001101xxx 32 268000h?26ffffh sa1-85 0 1 1001110xxx 32 270000h?277fffh sa1-86 0 1 1001111xxx 32 278000h?27ffffh sa1-87 0 1 1010000xxx 32 280000h?287fffh sa1-88 0 1 1010001xxx 32 288000h?28ffffh sa1-89 0 1 1010010xxx 32 290000h?297fffh sa1-90 0 1 1010011xxx 32 298000h?29ffffh sa1-91 0 1 1010100xxx 32 2a0000h?2a7fffh sa1-92 0 1 1010101xxx 32 2a8000h?2affffh sa1-93 0 1 1010110xxx 32 2b0000h?2b7fffh sa1-94 0 1 1010111xxx 32 2b8000h?2bffffh sa1-95 0 1 1011000xxx 32 2c0000h?2c7fffh sa1-96 0 1 1011001xxx 32 2c8000h?2cffffh sa1-97 0 1 1011010xxx 32 2d0000h?2d7fffh sa1-98 0 1 1011011xxx 32 2d8000h?2dffffh sa1-99 0 1 1011100xxx 32 2e0000h?2e7fffh sa1-100 0 1 1011101xxx 32 2e8000h?2effffh sa1-101 0 1 1011110xxx 32 2f0000h?2f7fffh sa1-102 0 1 1011111xxx 32 2f8000h?2fffffh sa1-103 0 1 1100000xxx 32 300000h?307fffh sa1-104 0 1 1100001xxx 32 308000h?30ffffh sa1-105 0 1 1100010xxx 32 310000h?317fffh sa1-106 0 1 1100011xxx 32 318000h?31ffffh sa1-107 0 1 1100100xxx 32 320000h?327fffh sa1-108 0 1 1100101xxx 32 328000h?32ffffh sa1-109 0 1 1100110xxx 32 330000h?337fffh sa1-110 0 1 1100111xxx 32 338000h?33ffffh sa1-111 0 1 1101000xxx 32 340000h?347fffh sa1-112 0 1 1101001xxx 32 348000h?34ffffh sa1-113 0 1 1101010xxx 32 350000h?357fffh sa1-114 0 1 1101011xxx 32 358000h?35ffffh sa1-115 0 1 1101100xxx 32 360000h?367fffh sa1-116 0 1 1101101xxx 32 368000h?36ffffh sa1-117 0 1 1101110xxx 32 370000h?377fffh sa1-118 0 1 1101111xxx 32 378000h?37ffffh sa1-119 0 1 1110000xxx 32 380000h?387fffh sa1-120 0 1 1110001xxx 32 388000h?38ffffh sa1-121 0 1 1110010xxx 32 390000h?397fffh sa1-122 0 1 1110011xxx 32 398000h?39ffffh sa1-123 0 1 1110100xxx 32 3a0000h?3a7fffh sa1-124 0 1 1110101xxx 32 3a8000h?3affffh sa1-125 0 1 1110110xxx 32 3b0000h?3b7fffh sa1-126 0 1 1110111xxx 32 3b8000h?3bffffh table 3. s29pl129j sector architecture (sheet 3 of 7) bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
26 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information bank 1b sa1-127 0 1 1111000xxx 32 3c0000h?3c7fffh sa1-128 0 1 1111001xxx 32 3c8000h?3cffffh sa1-129 0 1 1111010xxx 32 3d0000h?3d7fffh sa1-130 0 1 1111011xxx 32 3d8000h?3dffffh sa1-131 0 1 1111100xxx 32 3e0000h?3e7fffh sa1-132 0 1 1111101xxx 32 3e8000h?3effffh sa1-133 0 1 1111110xxx 32 3f0000h?3f7fffh sa1-134 0 1 1111111xxx 32 3f8000h?3fffffh bank 2a sa2-0 1 0 0000000xxx 32 000000h?007fffh sa2-1 1 0 0000001xxx 32 008000h?00ffffh sa2-2 1 0 0000010xxx 32 010000h?017fffh sa2-3 1 0 0000011xxx 32 018000h?01ffffh sa2-4 1 0 0000100xxx 32 020000h?027fffh sa2-5 1 0 0000101xxx 32 028000h?02ffffh sa2-6 1 0 0000110xxx 32 030000h?037fffh sa2-7 1 0 0000111xxx 32 038000h?03ffffh sa2-8 1 0 0001000xxx 32 040000h?047fffh sa2-9 1 0 0001001xxx 32 048000h?04ffffh sa2-10 1 0 0001010xxx 32 050000h?057fffh sa2-11 1 0 0001011xxx 32 058000h?05ffffh sa2-12 1 0 0001100xxx 32 060000h?067fffh sa2-13 1 0 0001101xxx 32 068000h?06ffffh sa2-14 1 0 0001110xxx 32 070000h?077fffh sa2-15 1 0 0001111xxx 32 078000h?07ffffh sa2-16 1 0 0010000xxx 32 080000h?087fffh sa2-17 1 0 0010001xxx 32 088000h?08ffffh sa2-18 1 0 0010010xxx 32 090000h?097fffh sa2-19 1 0 0010011xxx 32 098000h?09ffffh sa2-20 1 0 0010100xxx 32 0a0000h?0a7fffh sa2-21 1 0 0010101xxx 32 0a8000h?0affffh sa2-22 1 0 0010110xxx 32 0b0000h?0b7fffh sa2-23 1 0 0010111xxx 32 0b8000h?0bffffh sa2-24 1 0 0011000xxx 32 0c0000h?0c7fffh sa2-25 1 0 0011001xxx 32 0c8000h?0cffffh sa2-26 1 0 0011010xxx 32 0d0000h?0d7fffh sa2-27 1 0 0011011xxx 32 0d8000h?0dffffh sa2-28 1 0 0011100xxx 32 0e0000h?0e7fffh sa2-29 1 0 0011101xxx 32 0e8000h?0effffh sa2-30 1 0 0011110xxx 32 0f0000h?0f7fffh sa2-31 1 0 0011111xxx 32 0f8000h?0fffffh sa2-32 1 0 0100000xxx 32 100000h?107fffh sa2-33 1 0 0100001xxx 32 108000h?10ffffh sa2-34 1 0 0100010xxx 32 110000h?117fffh sa2-35 1 0 0100011xxx 32 118000h?11ffffh table 3. s29pl129j sector architecture (sheet 4 of 7) bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 27 advance information bank 2a sa2-36 1 0 0100100xxx 32 120000h?127fffh sa2-37 1 0 0100101xxx 32 128000h?12ffffh sa2-38 1 0 0100110xxx 32 130000h?137fffh sa2-39 1 0 0100111xxx 32 138000h?13ffffh sa2-40 1 0 0101000xxx 32 140000h?147fffh sa2-41 1 0 0101001xxx 32 148000h?14ffffh sa2-42 1 0 0101010xxx 32 150000h?157fffh sa2-43 1 0 0101011xxx 32 158000h?15ffffh bank 2a sa2-44 1 0 0101100xxx 32 160000h?167fffh sa2-45 1 0 0101101xxx 32 168000h?16ffffh sa2-46 1 0 0101110xxx 32 170000h?177fffh sa2-47 1 0 0101111xxx 32 178000h?17ffffh sa2-48 1 0 0110000xxx 32 180000h?187fffh sa2-49 1 0 0110001xxx 32 188000h?18ffffh sa2-50 1 0 0110010xxx 32 190000h?197fffh sa2-51 1 0 0110011xxx 32 198000h?19ffffh sa2-52 1 0 0110100xxx 32 1a0000h?1a7fffh sa2-53 1 0 0110101xxx 32 1a8000h?1affffh sa2-54 1 0 0110110xxx 32 1b0000h?1b7fffh sa2-55 1 0 0110111xxx 32 1b8000h?1bffffh sa2-56 1 0 0111000xxx 32 1c0000h?1c7fffh sa2-57 1 0 0111001xxx 32 1c8000h?1cffffh sa2-58 1 0 0111010xxx 32 1d0000h?1d7fffh sa2-59 1 0 0111011xxx 32 1d8000h?1dffffh sa2-60 1 0 0111100xxx 32 1e0000h?1e7fffh sa2-61 1 0 0111101xxx 32 1e8000h?1effffh sa2-62 1 0 0111110xxx 32 1f0000h?1f7fffh sa2-63 1 0 0111111xxx 32 1f8000h?1fffffh sa2-64 1 0 1000000xxx 32 200000h?207fffh sa2-65 1 0 1000001xxx 32 208000h?20ffffh sa2-66 1 0 1000010xxx 32 210000h?217fffh sa2-67 1 0 1000011xxx 32 218000h?21ffffh sa2-68 1 0 1000100xxx 32 220000h?227fffh sa2-69 1 0 1000101xxx 32 228000h?22ffffh sa2-70 1 0 1000110xxx 32 230000h?237fffh sa2-71 1 0 1000111xxx 32 238000h?23ffffh sa2-72 1 0 1001000xxx 32 240000h?247fffh sa2-73 1 0 1001001xxx 32 248000h?24ffffh sa2-74 1 0 1001010xxx 32 250000h?257fffh sa2-75 1 0 1001011xxx 32 258000h?25ffffh sa2-76 1 0 1001100xxx 32 260000h?267fffh sa2-77 1 0 1001101xxx 32 268000h?26ffffh sa2-78 1 0 1001110xxx 32 270000h?277fffh sa2-79 1 0 1001111xxx 32 278000h?27ffffh table 3. s29pl129j sector architecture (sheet 5 of 7) bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
28 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information bank 2a sa2-80 1 0 1010000xxx 32 280000h?287fffh sa2-81 1 0 1010001xxx 32 288000h?28ffffh sa2-82 1 0 1010010xxx 32 290000h?297fffh sa2-83 1 0 1010011xxx 32 298000h?29ffffh sa2-84 1 0 1010100xxx 32 2a0000h?2a7fffh sa2-85 1 0 1010101xxx 32 2a8000h?2affffh sa2-86 1 0 1010110xxx 32 2b0000h?2b7fffh sa2-87 1 0 1010111xxx 32 2b8000h?2bffffh sa2-88 1 0 1011000xxx 32 2c0000h?2c7fffh sa2-89 1 0 1011001xxx 32 2c8000h?2cffffh sa2-90 1 0 1011010xxx 32 2d0000h?2d7fffh sa2-91 1 0 1011011xxx 32 2d8000h?2dffffh sa2-92 1 0 1011100xxx 32 2e0000h?2e7fffh sa2-93 1 0 1011101xxx 32 2e8000h?2effffh sa2-94 1 0 1011110xxx 32 2f0000h?2f7fffh sa2-95 1 0 1011111xxx 32 2f8000h?2fffffh bank 2b sa2-96 1 0 1100000xxx 32 300000h?307fffh sa2-97 1 0 1100001xxx 32 308000h?30ffffh sa2-98 1 0 1100010xxx 32 310000h?317fffh sa2-99 1 0 1100011xxx 32 318000h?31ffffh sa2-100 1 0 1100100xxx 32 320000h?327fffh sa2-101 1 0 1100101xxx 32 328000h?32ffffh sa2-102 1 0 1100110xxx 32 330000h?337fffh sa2-103 1 0 1100111xxx 32 338000h?33ffffh sa2-104 1 0 1101000xxx 32 340000h?347fffh sa2-105 1 0 1101001xxx 32 348000h?34ffffh sa2-106 1 0 1101010xxx 32 350000h?357fffh sa2-107 1 0 1101011xxx 32 358000h?35ffffh sa2-108 1 0 1101100xxx 32 360000h?367fffh sa2-109 1 0 1101101xxx 32 368000h?36ffffh sa2-110 1 0 1101110xxx 32 370000h?377fffh sa2-111 1 0 1101111xxx 32 378000h?37ffffh sa2-112 1 0 1110000xxx 32 380000h?387fffh sa2-113 1 0 1110001xxx 32 388000h?38ffffh sa2-114 1 0 1110010xxx 32 390000h?397fffh sa2-115 1 0 1110011xxx 32 398000h?39ffffh sa2-116 1 0 1110100xxx 32 3a0000h?3a7fffh sa2-117 1 0 1110101xxx 32 3a8000h?3affffh sa2-118 1 0 1110110xxx 32 3b0000h?3b7fffh sa2-119 1 0 1110111xxx 32 3b8000h?3bffffh sa2-120 1 0 1111000xxx 32 3c0000h?3c7fffh sa2-121 1 0 1111001xxx 32 3c8000h?3cffffh sa2-122 1 0 1111010xxx 32 3d0000h?3d7fffh sa2-123 1 0 1111011xxx 32 3d8000h?3dffffh table 3. s29pl129j sector architecture (sheet 6 of 7) bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 29 advance information autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, th rough identifier codes outp ut on dq7?dq0. this mode is primarily intended for programming eq uipment to automatica lly match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on ad - dress pin a9. address pins must be as shown in ta b l e 5 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. ta b l e 5 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the correspondi ng identifier code on dq7?dq0. how - ever, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system with - out access to high voltage on the a9 pin. the command sequence is illustrated in ta b l e 12 . note: if a bank address (ba) (on address bits a21 ? a19 ) is asserted during the third write cycle of the autose lect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. to access the autoselect codes in-system, the host system can issue the autose - lect command via the command register, as shown in ta b l e 12 . this method does not require v id . see ?autoselect command sequence? on page 46 for more information. bank 2b sa2-124 1 0 1111100xxx 32 3e0000h?3e7fffh sa2-125 1 0 1111101xxx 32 3e8000h?3effffh sa2-126 1 0 1111110xxx 32 3f0000h?3f7fffh sa2-127 1 0 1111111000 4 3f8000h?3f8fffh sa2-128 1 0 1111111001 4 3f9000h?3f9fffh sa2-129 1 0 1111111010 4 3fa000h?3fafffh sa2-130 1 0 1111111011 4 3fb000h?3fbfffh sa2-131 1 0 1111111100 4 3fc000h?3fcfffh sa2-132 1 0 1111111101 4 3fd000h?3fdfffh sa2-133 1 0 1111111110 4 3fe000h?3fefffh sa2-134 1 0 1111111111 4 3ff000h?3fffffh ta b l e 4 . secured silicon sector addresses sector size address range factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh table 3. s29pl129j sector architecture (sheet 7 of 7) bank sector ce1# ce2# sector address (a21- a12) sector size (kwords) address range (x16)
30 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information legend: l = logic low = v il , h = logic high = v ih , ba = bank address, sa = sector address, x = don?t care. note: the autoselect codes may also be accessed in-system via command sequences ta b l e 5 . autoselect codes for pl129j description ce1# ce2# oe# we# a21 to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq0 manufacturer id : spansion products l h l h x x v i d x l l x l l l l 0001h h l device id read cycle 1 l h l h x x v i d x l l l l l l h 227eh h l read cycle 2 l h h h h l 2221h h l read cycle 3 l h h h h h 2200h h l sector protection verification l h l h sa x v i d x l l l l l h l 0001h (protected), 0000h (unprotected) h l secured silicon indicator bit (dq7, dq6) l h l h x x v i d x x l x l l h h dq7=1 (factory locked), dq6=1 (factory and customer locked) h l
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 31 advance information ta b l e 6 . pl129j boot sector/sector block ad dresses for protection/unprotection ce1# control ce2# control sector group a21-12 sector/sector block size sector group a21-12 sector/sector block size sa1-0 0000000000 4 kwords sa2-0?sa2-3 00000xxxxx 128 (4x32) kwords sa1-1 0000000001 4 kwords sa2-4?sa2-7 00001xxxxx 128 (4x32) kwords sa1-2 0000000010 4 kwords sa2-8?sa2-11 00010xxxxx 128 (4x32) kwords sa1-3 0000000011 4 kwords sa2-12?sa2-15 00011xxxxx 128 (4x32) kwords sa1-4 0000000100 4 kwords sa2-16?sa2-19 00100xxxxx 128 (4x32) kwords sa1-5 0000000101 4 kwords sa2-20?sa2-23 00101xxxxx 128 (4x32) kwords sa1-6 0000000110 4 kwords sa2-24?sa2-27 00110xxxxx 128 (4x32) kwords sa1-7 0000000111 4 kwords sa2-28?sa2-31 00111xxxxx 128 (4x32) kwords sa1-8 0000001xxx 32 kwords sa2-32?sa2-35 01000xxxxx 128 (4x32) kwords sa1-9 0000010xxx 32 kwords sa2-36?sa2-39 01001xxxxx 128 (4x32) kwords sa1-10 0000011xxx 32 kwords sa2-40?sa2-43 01010xxxxx 128 (4x32) kwords sa1-11 - sa1-14 00001xxxxx 128 (4x32) kwords sa2-44?sa2-47 01011xxxxx 128 (4x32) kwords sa1-15 - sa1-18 00010xxxxx 128 (4x32) kwords sa2-48?sa2-51 01100xxxxx 128 (4x32) kwords sa1-19 - sa1-22 00011xxxxx 128 (4x32) kwords sa2-52?sa2-55 01101xxxxx 128 (4x32) kwords sa1-23 - sa1-26 00100xxxxx 128 (4x32) kwords sa2-56?sa2-59 01110xxxxx 128 (4x32) kwords sa1-27 - sa1-30 00101xxxxx 128 (4x32) kwords sa2-60?sa2-63 01111xxxxx 128 (4x32) kwords sa1-31 - sa1-34 00110xxxxx 128 (4x32) kwords sa2-64?sa2-67 10000xxxxx 128 (4x32) kwords sa1-35 - sa1-38 00111xxxxx 128 (4x32) kwords sa2-68?sa2-71 10001xxxxx 128 (4x32) kwords sa1-39 - sa1-42 01000xxxxx 128 (4x32) kwords sa2-72?sa2-75 10010xxxxx 128 (4x32) kwords sa1-43 - sa1-46 01001xxxxx 128 (4x32) kwords sa2-76?sa2-79 10011xxxxx 128 (4x32) kwords sa1-47 - sa1-50 01010xxxxx 128 (4x32) kwords sa2-80?sa2-83 10100xxxxx 128 (4x32) kwords sa1-51 - sa1-54 01011xxxxx 128 (4x32) kwords sa2-84?sa2-87 10101xxxxx 128 (4x32) kwords sa1-55 - sa1-58 01100xxxxx 128 (4x32) kwords sa2-88?sa2-91 10110xxxxx 128 (4x32) kwords sa1-59 - sa1-62 01101xxxxx 128 (4x32) kwords sa2-92?sa2-95 10111xxxxx 128 (4x32) kwords sa1-63 - sa1-66 01110xxxxx 128 (4x32) kwords sa2-96?sa2-99 11000xxxxx 128 (4x32) kwords sa1-67 - sa1-70 01111xxxxx 128 (4x32) kwords sa2-100?sa2-103 11001xxxxx 128 (4x32) kwords sa1-71 - sa1-74 10000xxxxx 128 (4x32) kwords sa2-104?sa2-107 11010xxxxx 128 (4x32) kwords sa1-75 - sa1-78 10001xxxxx 128 (4x32) kwords sa2-108?sa2-111 11011xxxxx 128 (4x32) kwords sa1-79 - sa1-82 10010xxxxx 128 (4x32) kwords sa2-112?sa2-115 11100xxxxx 128 (4x32) kwords sa1-83 - sa1-86 10011xxxxx 128 (4x32) kwords sa2-116?sa2-119 11101xxxxx 128 (4x32) kwords sa1-87 - sa1-90 10100xxxxx 128 (4x32) kwords sa2-120?sa2-123 11110xxxxx 128 (4x32) kwords sa1-91 - sa1-94 10101xxxxx 128 (4x32) kwords sa2-124 1111100xxx 32 kwords sa1-95 - sa1-98 10110xxxxx 128 (4x32) kwords sa2-125 1111101xxx 32 kwords sa1-99 - sa1-102 10111xxxxx 128 (4x32) kwords sa2-126 1111110xxx 32 kwords sa1-103 - sa1-106 11000xxxxx 128 (4x32) kwords sa2-127 1111111000 4 kwords sa1-107 - sa1-110 11001xxxxx 128 (4x32) kwords sa2-128 1111111001 4 kwords sa1-111 - sa1-114 11010xxxxx 128 (4x32) kwords sa2-129 1111111010 4 kwords sa1-115 - sa1-118 11011xxxxx 128 (4x32) kwords sa2-130 1111111011 4 kwords sa1-119 - sa1-122 11100xxxxx 128 (4x32) kwords sa2-131 1111111100 4 kwords sa1-123 - sa1-126 11101xxxxx 128 (4x32) kwords sa2-132 1111111101 4 kwords sa1-127 - sa1-130 11110xxxxx 128 (4x32) kwords sa2-133 1111111110 4 kwords sa1-131 - sa1-134 11111xxxxx 128 (4x32) kwords sa2-134 1111111111 4 kwords
32 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information selecting a sector protection mode the device is shipped with all sectors unprotected. optional spansion program - ming services enable programming and prot ecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a se ctor is protected or unprotected. see ?se - cured silicon sector addresses? on page 29 for details. sector protection the pl129j features several levels of se ctor protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled pro - tection method. password sector protection a highly sophisticated protection meth od that requires a password before changes to certain sectors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in sectors sa1- 133, sa1-134, sa2-0 and sa2-1. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the pers istent sector protec tion mode. the cus - tomer must then choose if the persistent or password protection method is most desirable. there are two one-time progra mmable non-volatile bits that define which sector protection method is used . if the persistent sector protection method is desired, programming the persistent sector protection mode locking bit permanently sets the devi ce to the persistent sector protection mode. if the password sector protection method is desired, programming the password mode locking bit permanently sets the device to the password sector protection mode. it is not possible to switch between th e two protection modes once a locking bit has been set. one of the two modes must be selected when the device is first ta b l e 7 . sector protection schemes dyb ppb ppb lock sector state 0 0 0 unprotected?ppb and dyb are changeable 0 0 1 unprotected?ppb not changeable, dyb is changeable 0 1 0 protected?ppb and dyb are changeable 1 0 0 1 1 0 0 1 1 protected?ppb not changeable, dyb is changeable 1 0 1 1 1 1
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 33 advance information programmed. this prevents a program or virus from later setting the password mode locking bit, which wo uld cause an unexpected shift from the default per - sistent sector protection mode in to the password protection mode. the device is shipped with all sectors unprotected. optional spansion program - ming services enable programming and prot ecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a se ctor is protected or unprotected. see au - toselect mode for details. persistent sector protection the persistent sector protection method replaces the 12 v controlled protection method in previous flash devices. this new method provides three different sec - tor protection states: ? persistently locked?the sector is protected and cannot be changed. ? dynamically locked?the sector is protected and can be changed by a simple command. ? unlocked?the sector is unprotected and can be changed by a simple com - mand. to achieve these states, three types of ?bits? are used: ? persistent protection bit ? persistent protection bit lock ? persistent sector protec tion mode locking bit persistent protection bit (ppb) a single persistent (non-volatile) protec tion bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). all 4 kword boot-block sectors have indivi dual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command. the device erases all ppbs in parallel. if any ppb requires erasure, the device must be instructed to prepro gram all of the sector ppbs prior to ppb erasure. oth - erwise, a previously erased sector ppbs can potentially be over-erased. the flash device does not have a built-in means of preventing sector ppbs over-erasure. persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lock ) is a global volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are changeable. there is only one ppb lock bit per devi ce. the ppb lock is cleared after power- up or hardware reset. there is no co mmand sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first shipped, the ppbs are cleared, the dybs are cleared, and ppb lock is defaulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not pro - tected). the protection state for each sect or is determined by the logical or of
34 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information the ppb and the dyb related to that sect or. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequence s, the dybs are set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. thes e states are called dynamic states be - cause it is very easy to switch ba ck and forth between the protected and unprotected conditions. this allows softwa re to easily protect sectors against in - advertent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficu lt to change, level of protection. the ppbs retain their state across power cycl es because the ppbs are non-volatile. in - dividual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also lim - ited to 100 erase cycles. the ppb lock bit adds an additional level of protection. once all ppbs are pro - grammed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase co mmands to the non-vo latile ppbs. in ef - fect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cy cle. system boot code can determine if any changes to the ppb are needed; for example, to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system operation. the wp#/acc write protect pin adds a final level of hardware protection to sec - tors sa1-133, sa1-134, sa2-0 and sa2-1. when this pin is low it is not possible to change the contents of these sector s. these sectors generally hold system boot code. the wp#/acc pin can prevent an y changes to the boot code that could override the choices made while setting up sector protection during system initialization. for customers who are concerned about ma licious viruses there is another level of security - the persistently locked state. to persistently protect a given sector or sector group, the ppbs associated with that sector need to be set to ?1?. once all ppbs are programmed to the desired settings, the ppb lock should be set to ?1?. setting the ppb lock automatically disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock ?freezes? the ppbs into their cur - rent state. the only way to clear the pp b lock is to go through a power cycle. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb write command se - quence is all that is necessary. the dy b write command for the dynamic sectors switch the dybs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled by either putting the device through a power-cycle, or hardware rese t. the ppbs can then be changed to re - flect the desired settings. setting the ppb lock bit once again lock the ppbs, and the device operates normally again. the best protection is achieved by exec uting the ppb lock bit set command early in the boot code, and protect the bo ot code by holding wp#/acc = vil. table 17 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector.
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 35 advance information in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until th e next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dyb then controls whether or not the se ctor is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sec - tor enables status polling for approximately 1 s before the device returns to read mode without having modified the conten ts of the protected sector. an erase command to a protected sector enables st atus polling for approximately 50 s after which the device returns to read mo de without having erased the protected sector. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing a dyb/ppb/ppb lock verify command to the device. there is an alter - native means of reading the protection st atus. take reset# to vil and hold we# at vih.(the high voltage a9 autoselect mo de also works for reading the status of the ppbs). scanning the addresses (a18?a 11) while (a6, a1, a0) = (0, 1, 0) pro - duces a logical ?1? code at device output dq0 for a protected sector or a ?0? for an unprotected sector. in this mode, the other addresses are don?t cares. address location with a1 = vil are reserved for autoselect manufacturer and device codes. persistent sector protection mode locking bit like the password mode locking bit, a pers istent sector protection mode locking bit exists to guarantee that the device re main in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. th is guarantees that a hacker could not place the device in password protection mode. password protection mode the password sector protection mode meth od allows an even higher level of se - curity than the persistent sector protec tion mode. there are two main differences between the persistent sector protection and the password sector protection mode: when the device is first powered on, or comes out of a reset cycle, the ppb lock bit set to the locked state, rather than cleared to the unlocked state. the only means to clear the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only addition al tool utilized in this method. once the password mode locking bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash de vice does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries al l possible combinations in order to crack the password.
36 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information password and password mode locking bit in order to select the password sector pr otection scheme, the customer must first program the password. the password may be correlated to the unique electronic serial number (esn) of the particular flas h device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: permanently sets the device to operate us ing the password protection mode. it is not possible to reverse this function. disables all further commands to the pass word region. all program, and read op - erations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the passwor d mode locking bit. more importantly, the user must be sure that the passw ord is correct when the password mode locking bit is set. due to th e fact that read operations are disabled, there is no means to verify what the password is afte rwards. if the password is lost after set - ting the password mode locking bit, there is not any way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password pr ogramming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persis - tent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its ow n memory space and is accessible through the use of the password program and verify commands (see ?password verify command?). the password function works in conjunction with the password mode locking bit, which when set, prev ents the password verify command from reading the contents of the passw ord on the pins of the device. write protect (wp#) the write protect feature provides a hard ware method of protecting the upper two and lower two sectors(pl127j: 0, 1, 268, and 269, pl064j: 0, 1, 140, and 141, pl032j: 0, 1, 76, and 77, pl1 29j: sa1-133, sa1-134,sa2-0 and sa2-1) without using v id . this function is provided by the wp# pin and overrides the pre - viously discussed method, ?high voltage sector protection? on page 37 . if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two outermost 4 kw ord sectors on both ends of the flash array independent of whether it was previously protected or unprotected. if the system asserts v ih on the wp#/acc pin, the de vice reverts the upper two and lower two sectors to whether they we re last set to be protected or unpro - tected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or un protected using the method described in ?high voltage sector protection? on page 37 . note that the wp#/acc pin must not be le ft floating or unconnected; inconsistent behavior of the device may result.
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 37 advance information persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power- up reset. if the password mode lock bit is also set after a hardware reset (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. assert - ing reset#, taking the device through a po wer-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1? when the password mode lock bit is not set. if the password mode locking bit is not se t, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set comma nd. once set the only means for clear - ing the ppb lock bit is by issuing a hard ware or power-up reset. the password unlock command is ignored in persistent protection mode. high voltage sector protection sector protection and unprotection may also be implemented using programming equipment. the procedure requires high voltage (v id ) to be placed on the re - set# pin. refer to figure 1 for details on this procedure. note that for sector unprotect, all unprotected sectors must firs t be protected prior to the first sector write cycle.
38 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information figure 1. in-system sector protection/s ector unprotection algorithms sector protect: write 60h to sector address with a7-a0 = 00000010 set up sector address wait 100 s verify sector protect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7-a0 = 01000010 set up first sector address wait 1.2 ms verify sector unprotect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 remove v id from reset# write reset command sector protect complete remove v id from reset# write reset command sector unprotect complete
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 39 advance information temporary sector unprotect this feature allows temporary unprotecti on of previously protected sectors to change data in-system. the sector unpr otect mode is activa ted by setting the reset# pin to v id . during this mode, formerly protected sectors can be pro - grammed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure 2 shows the algorithm, and figure 21 shows the timing diagrams, for this feature. while ppb lock is set, the device cannot enter the temporary sector un - protection mode. secured silicon sector flash memory region the secured silicon sector feature provid es a flash memory region that enables permanent part identification through an electronic serial number (esn) the 128-word secured silicon sector is divided into 64 factory-lockable words that can be programmed and locked by the cu stomer. the secured silicon sector is located at addresses 000000h-00007fh in both persistent protection mode and password protection mode. indicator bits dq6 and dq7 are used to indicate the factory-locked and customer locked status of the part. the system accesses the secured silico n sector through a command sequence (see ?enter secured silicon sector/exit secured silicon sector command se - quence? on page 46 ). after the system has writ ten the enter secured silicon sector command sequence, it may read th e secured silicon sector by using the addresses normally occupied by the boot sectors. this mode of operation contin - ues until the system issues the exit se cured silicon sector command sequence, or until power is removed from the device . on power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. note that the acc function and unlock bypa ss modes are not available when the se - cured silicon sector is enabled. notes: 1. all protected sectors are unprotected (if wp#/acc = v il , upper two and lower two sectors remain protected). 2. all previously protected sect ors are protected once again figure 2. temporary sector unprotect operation start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
40 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information factory-locked area (64 words) the factory-locked area of the secu red silicon sector (000000h-00003fh) is locked when the part is shipped, whethe r or not the area was programmed at the factory. the secured silicon sector fact ory-locked indicator bit (dq7) is perma - nently set to a ?1?. optional spansion programming services can program the factory-locked area with a random esn, a customer-defined code, or any combi - nation of the two. because only fasl can program and protect the factory-locked area, this method ensures the security of the esn once the product is shipped to the field. contact your local sales office for details on using spansion?s program - ming services. note that the acc func tion and unlock bypass modes are not available when the secured silicon sector is enabled. customer-lockable area (64 words) the customer-lockable area of the secure d silicon sector (000040h-00007fh) is shipped unprotected, which allows the cu stomer to program and optionally lock the area as appropriate for the application. the secured silicon sector customer- locked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secured silicon protection bit program command. the secured sil - icon sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass func - tions are not available when programming the secured silicon sector. the customer-lockable secured silicon se ctor area can be protected using one of the following procedures: ? write the three-cycle enter secured silicon sector region command se - quence, and then follow the in-system sector protect algorithm as shown in figure 1 , except that reset# may be at either v ih or v id . this allows in-sys - tem protection of the se cured silicon sector region without raising any de - vice pin to a high voltage. note that this method is only applicable to the secured silicon sector. ? to verify the protect/unprotect status of the secured silicon sector, follow the algorithm shown in figure 3 . once the secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array. the secured silicon sector lock must be used with caution since, once locked, there is no procedure available for unlocki ng the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. secured silicon sector protection bits the secured silicon sector protection bits prevent programming of the secured silicon sector memory area. once set, the secured silicon sector memory area contents are non-modifiable.
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 41 advance information hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadve rtent writes. in addition, the following hardware data protection measures prev ent accidental eras ure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transi tions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro - tects data during v cc power-up and power-down. th e command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the cont rol pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce1#, ce2# or we# do not ini - tiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce1# = ce2# = v ih or we# = v ih . to initiate a write cycle, ce1# / ce2# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# (ce1#, ce2# in pl129j) = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically rese t to the read mode on power-up. figure 3. secured silicon sector protect verify write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
42 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information common flash memory interface (cfi) the common flash interface (cfi) specific ation outlines device and host system software interrogation hand shake, which allows specific vendor-specified soft - ware algorithms to be used for entire fa milies of devices. software support can then be device-independent, jedec id -independent, and forward- and back - ward-compatible for the specified flash device families. flash vendors can standardize their existing interfac es for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time th e device is ready to read array data. the system can read cfi informat ion at the addresses given in ta b l e 8 , ta b l e 9 , ta b l e 10 , and ta b l e 11 . to terminate reading cfi data, the system must write the reset command. the cfi query mode is not accessible when the device is exe - cuting an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the au - toselect mode. the device enters the cf i query mode, and the system can read cfi data at the addresses given in ta b l e 8 , ta b l e 9 , ta b l e 10 , and ta b l e 11 . the system must write the reset command to re turn the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100. contact your local sales office for copies of these documents. ta b l e 8 . cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists)
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 43 advance information ta b l e 9 . system interface string addresses data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0003h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) ta b l e 1 0 . device geometry definition addresses data description 27h 0018h (pl129j) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specifica tion or cfi publication 100) 31h 00fdh (pl129j) erase block region 2 information (refer to the cfi specifica tion or cfi publication 100) 32h 33h 34h 0000h 0000h 0001h 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specifica tion or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specifica tion or cfi publication 100) ta b l e 1 1 . primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri?
44 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information 43h 0031h major version number, ascii (refle cts modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h tbd address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h (plxxxj) sector protect/unprotect scheme 07 = advanced sector protection 4ah 00e7h (pl129j) simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h (plxxxj) page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = uniform device, 01h = both top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h (pl129j) bank 1 region information x = number of sectors in bank 1 59h 0060h (pl129j) bank 2 region information x = number of sectors in bank 2 5ah 0060h (pl129j) bank 3 region information x = number of sectors in bank 3 5bh 0027h (pl129j) bank 4 region information x = number of sectors in bank 4 table 11. primary vendor-specific extended query (continued) addresses data description
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 45 advance information command definitions writing specific address and data comma nds or sequences into the command register initiates device operations. ta b l e 12 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset com - mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce# (ce1# / ce2# in pl129j), whichever happens later. all data is latched on the rising edge of we# or ce# (ce1# / ce2# in pl129j), whichever happens first. see ac characteristics for timing diagrams. reading array data the device is automatically set to readin g array data after device power-up. no commands are required to retrieve data. ea ch bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspe nd command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data . after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see ?erase suspend/erase re - sume commands? on page 50 for more information. the system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if dq5 goes high during an active program or erase opera - tion, or if the bank is in the autoselect mode. see ? reset command ,? for more information. see ?requirements for reading array data? on page 19 in ?device bus opera - tions? for more information. the ac characteristics table provides the read parameters, and figure 12 shows the timing diagram. reset command writing the reset command resets the bank s to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys - tem was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming be gins. this resets the bank to which the system was writing to the read mode . if the program command sequence is written to a bank that is in the eras e suspend mode, writing the reset command returns that bank to the erase-suspen d-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autosele ct mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the re set command returns that bank to the erase-suspend-read mode.
46 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the re ad mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manu - facturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-su spend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initia ted by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au - toselect command. the bank then enters the autoselect mode. the system may read any number of autoselect codes with out reinitiating the command sequence. ta b l e 12 shows the address and data requir ements. to determine sector protec - tion information, the system must write to the appropri ate bank address (ba) and sector address (sa). the system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank wa s previously in erase suspend). enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing a ran - dom, eight word electronic serial numb er (esn). the system can access the secured silicon sector region by issuing the three-cycle enter secured silicon sector command sequence. the device co ntinues to access the secured silicon sector region until the system issues th e four-cycle exit secured silicon sector command sequence. the exit secured sili con sector command sequence returns the device to normal operation. the secure d silicon sector is not accessible when the device is executing an embedded program or embedded erase algorithm. ta b l e 12 shows the address and data requirem ents for both command sequences. also see, ?secured silicon sector flash memory region? on page 39 for further in - formation. note: the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. word program command sequence programming is a four-bus-cycle operat ion. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com - mand. the program address and data are wr itten next, which in turn initiate the embedded program algorithm. the system is not required to provide further con - trols or timings. the device automatically provides in ternally generated program pulses and verifies the programmed cell margin. ta b l e 12 shows the address and data requirements for the program command sequence. note that the secured silicon sector, autoselect, and cfi func tions are unavailable when a [program/ erase] operation is in progress. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no long er latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. see ?write operation status? on page 56 for information on these status bits.
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 47 advance information any commands written to the device du ring the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. note that the secured silicon sector, autoselect and cfi functi ons are unavailable when the secured sil - icon sector is enabled. programming is allowed in any sequ ence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read shows that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the syst em to program data to a bank faster than using the standard program command sequence. the unlock bypass com - mand sequence is initiated by first writin g two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two- cycle unlock bypass program command sequence is all that is required to progra m in this mode. the first cycle in this se - quence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. a dditional data is programmed in the same manner. this mode dispenses with th e initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. ta b l e 12 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by - pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. ( ta b l e 13 ) the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, th e device automatically en - ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the devi ce uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device damage may result. in addition, the wp#/acc pi n must not be left floating or uncon - nected; inconsistent behavior of the device may result. figure 4 illustrates the algorithm for the program operation. see the erase/pro - gram operations table in ac characteristics for parameters, and figure 14 for timing diagrams.
48 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini - tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to er ase. the embedded erase algorithm auto - matically preprograms and verifies the enti re memory for an all zero data pattern prior to electrical erase. the system is no t required to provide any controls or tim - ings during these operations. ta b l e 12 shows the address an d data requirements for the chip erase command sequence. when the embedded erase algorithm is comp lete, that bank returns to the read mode and addresses are no longer latche d. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to ?write op - eration status? on page 56 for information on these status bits. any commands written during the chip erase operation are ignored. note that se - cured silicon sector, autoselect, and cfi functions are unavailable when a [program/erase] operation is in progress. however, note that a hardware reset immediately terminates the erase operatio n. if that occurs, the chip erase com - mand sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase operation. see the erase/program operations tables in ac characteristics for parameters, and figure 16 for timing diagrams. note: see table 12 for program command sequence. figure 4. program operation start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 49 advance information sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi - tional unlock cycles are written, and ar e then followed by the address of the sector to be erased, and the sector erase command. ta b l e 12 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em - bedded erase algorithm automatically prog rams and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timi ngs during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period , additional sector addresses and sector erase com - mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address an d command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if any com - mand other than 30h, b0h, f0h is input during the time-out period, the normal operation cannot be guaranteed. the system must rewrite the com - mand sequence and any additional addresses and commands. note that secured silicon sector, autoselect, and cfi func tions are unavailable when a [program/ erase] operation is in progress. the system can monitor dq3 to determine if the sector erase timer has timed out (see ?dq3: sector erase timer? on page 61 ). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is co mplete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the syst em can read data from the non-erasing bank. the system can determine the stat us of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. see ?write operation status? on page 56 for information on these status bits. once the sector erase operation has begu n, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im - mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated on ce that bank has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase operation. see the erase/program operations tables in ac characteristics for parameters, and figure 16 for timing diagrams.
50 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or pr ogram data to, any sector not selected for erasure. the bank address is required when writing this command. this com - mand is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. how - ever, when the erase suspend command is written during the sector erase time-out, the device immedi ately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. after the erase operation has been suspe nded, the bank enters the erase-sus - pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta - tus information on dq7?d q0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is acti vely erasing or is erase-suspended. see ?write operation status? on page 56 for information on these status bits. after an erase-suspended program operatio n is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program notes: 1. see table 12 for erase command sequence. 2. see ?dq3: sector erase timer? on page 61 for information on the sector erase timer. figure 5. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 51 advance information operation using the dq7 or dq6 status bits, just as in the standard word program operation. see ?write operation status? on page 56 for more information. in the erase-suspend-read mode, the syst em can also issue the autoselect com - mand sequence. the device allows readin g autoselect codes even at addresses within erasing sectors, since the codes ar e not stored in the memory array. when the device exits the autoselect mode, th e device reverts to the erase suspend mode, and is ready for another valid operation. see ?secured silicon sector ad - dresses? on page 29 and ?autoselect command sequence? on page 46 for details. to resume the sector erase operation, the system must write the erase resume command (address bits are don?t care). the bank address of the erase-sus - pended bank is required when writin g this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. password program command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. four password program commands ar e required to program the password. the system must enter the unlock cycl e, password program command (38h) and the program address/data for each port ion of the password when programming. there are no provisions for entering th e 2-cycle unlock cycle, the password pro - gram command, and all the pa ssword data. there is no special addressing order required for programming the password. also, when the password is undergoing programming, simultaneous operation is disabled. read operations to any mem - ory location will return the programming status. once programming is complete, the user must issue a read/reset command to return the device to normal oper - ation. once the password is written and verified, the password mode locking bit must be set in order to prevent verifi cation. the password program command is only capable of programming ?0?s. progra mming a ?1? after a cell is programmed as a ?0? results in a time-out by the em bedded program algorithm? with the cell remaining as a ?0?. the password is all on es when shipped from the factory. all 64-bit password combinations are valid as a password. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will always dr ive all f?s onto the dq data bus. the password verify command is permitte d if the secured silicon sector is en - abled. also, the device will not operat e in simultaneous operation when the password verify command is executed. only the password is returned regardless of the bank address. the lower two address bits (a1-a0) are valid during the password verify. writing the read/reset command returns the device back to normal operation. password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, wh ich prevents further verifies or updates to the password. once programmed, the password protection mode locking bit cannot be erased! if the password protecti on mode locking bit is verified as pro - gram without margin, the password pr otection mode locking bit program
52 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information command can be executed to improve th e program margin. once the password protection mode locking bit is programm ed, the persistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode lo cking bit, which prevents the password mode locking bit from ever being programmed. if the persistent sector protec - tion mode locking bit is verified as programmed without marg in, the persistent sector protection mode locking bit prog ram command should be reissued to im - prove program margin. by disabling the program circuitry of the password mode locking bit, the device is forced to rema in in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program command is acco mplished by writing the read/reset command. secured silicon sector protection bit program command the secured silicon sector protection bit program command programs the se - cured silicon sector protection bit, wh ich prevents the secured silicon sector memory from being cleared. if the secured silicon sector protection bit is verified as programmed without margin, the secured silicon sector protection bit pro - gram command should be reissu ed to improve program margin. exiting the v cc - level secured silicon sector protection bit program command is accomplished by writing the read/reset command. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared unless the device is taken through a powe r-on clear or the password unlock com - mand is executed. upon setting the ppb lo ck bit, the ppbs ar e latched into the dybs. if the password mode locking bit is se t, the ppb lock bit status is reflected as set, even after a power-on reset cycl e. exiting the ppb lock bit set command is accomplished by writing the read/res et command (only in the persistent pro - tection mode). dyb write command the dyb write command is used to set or clear a dyb for a given sector. the high order address bits (amax?a12) are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dybs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hardware reset.exiting the dyb write command is accomplished by writing the read/reset command. password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become accessible for modification. the exact password must be entered in order for the unlocking function to occur. this command ca nnot be issued any faster than 2 s at a time to prevent a hacker from running through all 64-bit combinations in an attempt
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 53 advance information to correctly match a password. if th e command is issued before the 2 s execu - tion window for each portion of the unlock, the command will be ignored. once the password unlock command is en tered, the ry/by# indicates that the device is busy. approximately 1 s is requ ired for each portion of the unlock. once the first portion of the password unlock completes (ry/by# is not low or dq6 does not toggle when read), the next part of the password is written. the system must thus monitor ry/by# or the status bits to confirm when to write the next portion of the password. seven cycles are required to successfully clear the ppb lock bit. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually programmed (but is bulk erased with the other ppbs). the specific sector address (a22?a12) are written at the same time as the program command 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after programming a ppb, two additional cycles are needed to determine whether the ppb has been programmed with ma rgin. if the ppb has been programmed without margin, the program command shou ld be reissued to improve the pro - gram margin. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. the ppb program command does not fo llow the embedded program algorithm. all ppb erase command the all ppb erase command is used to eras e all ppbs in bulk. there is no means for individually erasing a specific ppb. unli ke the ppb program, no specific sector address is required. however, when the ppb erase command is written all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the command will ti me-out without eras ing the ppbs. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppb s has been erased without margin, the erase command should be reissued to improve the program margin. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-erasure may occur making it difficult to program the ppb at a later ti me. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. dyb write command the dyb write command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is protected regardless of the value of the dy b. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dybs. the bank address is latched when the command is written. ppb lock bit set command the ppb lock bit set command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is protected regardless of the value of the dyb. if the ppb is cleared, setting the
54 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dybs. the bank address is latched when the command is written. command the programming of either the ppb or dyb for a given sector or sector group can be verified by writing a sector protection status command to the device. note that there is no single command to independently verify the programming of a dyb for a given sector group. command definitions tables legend: ba = address of bank switching to autoselect mode, by pass mode, or erase operation. determined by amax:a19. pa = program address (amax:a0). addresses latch on fall ing edge of we# or ce1#/c e2# pulse, whichever happens later. pd = program data (dq15:dq0) written to location pa. da ta latches on rising edge of we# or ce1#/ce2# pulse, whichever happens first. ra = read address (amax:a0). rd = read data (dq15:dq0) from location ra. sa = sector address (amax:a12) for veri fying (in autoselect mode) or erasing. wd = write data. see ?configuration register? definition for specific write data. data latc hed on rising edge of we#. x = don?t care notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycl es. all other cycles are write operations. ta b l e 1 2 . memory array command definitions command (notes) cycles bus cycles (notes 1 ? 4 ) addr data addr data addr data addr data addr data addr data read ( note 5 ) 1 ra rd reset ( note 6 ) 1 xxx f0 autoselect ( note 7 ) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 01 device id ( note 10 ) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba) x0e ( note 10 ) (ba) x0f ( note 10 ) secured silicon sector factory protect ( note 8 ) 4 555 aa 2aa 55 (ba) 555 90 x03 ( note 8 ) sector group protect verify ( note 9 ) 4 555 aaa 2aa 55 (ba) 555 90 (sa) x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend ( note 11 ) 1 ba b0 program/erase resume ( note 12 ) 1 ba 30 cfi query ( note 13 ) 1 55 98 accelerated program ( note 15 ) 2 xx a0 pa pd unlock bypass entry ( note 15 ) 3 555 aa 2aa 55 555 20 unlock bypass program ( note 15 ) 2 xx a0 pa pd unlock bypass erase ( note 15 ) 2 xx 80 xx 10 unlock bypass cfi (notes 13 , 15 ) 1 xx 98 unlock bypass reset ( note 15 ) 2 xxx 90 xxx 00
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 55 advance information 4. during unlock and command cycles, when lower address bits ar e 555 or 2aah as shown in tabl e, address bits higher than a11 (except where ba is requ ired) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if previously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is providing status information). 7. fourth cycle of autoselect command sequence is a read cycle. system must provide bank address to obtain manufacturer id or device id information. see ?autoselect command sequence? on page 46 for more information. 8. the data is dq6=1 for factory and customer locked and dq7=1 for factory locked. 9. the data is 00h for an unpro tected sector group and 01h for a protected sector group. 10. device id must be read across cycles 4, 5, and 6. pl129j (x0eh = 2221h, x0fh = 2200h). 11. system may read and program in non-er asing sectors, or enter autoselect mode , when in program/erase suspend mode. program/erase suspend command is valid only during a sector erase operation, and requires bank address. 12. program/erase resume co mmand is valid only during erase susp end mode, and requires bank address. 13. command is valid when device is ready to read ar ray data or when device is in autoselect mode. 14. wp#/acc must be at v id during the entire operation of command. 15. unlock bypass entry command is required prior to any unlock bypass operation. unlock bypass reset command is required to return to the reading array. legend: dyb = dynamic protection bit ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit ta b l e 1 3 . sector protection command definitions command (notes) cycles bus cycles (notes 1 - 4 ) addr data addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit 4 555 aa 2aa 55 555 90 xx 00 secured silicon protection bit program (notes 5 , 6 ) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd (0) secured silicon protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd (0) password program (notes 5 , 7 , 8 ) 4 555 aa 2aa 55 555 38 xx [0-3] pd [0-3] password verify (notes 6 , 8 , 9 ) 4 555 aa 2aa 55 555 c8 pwa [0-3] pwd [0-3] password unlock (notes 7 , 10 , 11 ) 7 555 aa 2aa 55 555 28 pwa [0] pwd [0] pwa [1] pwd [1] pwa [2] pwd [2] pwa [3] pwd [3] ppb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 (sa) wp 68 (sa) wp 48 (sa) wp rd (0) ppb status 4 555 aa 2aa 55 555 90 (sa) wp rd (0) all ppb erase (notes 5 , 6 , 13 , 14 ) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa) wp rd (0) ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status ( note 15 ) 4 555 aa 2aa 55 555 58 sa rd (1) dyb write ( note 7 ) 4 555 aa 2aa 55 555 48 sa x1 dyb erase ( note 7 ) 4 555 aa 2aa 55 555 48 sa x0 dyb status ( note 6 ) 4 555 aa 2aa 55 555 58 sa rd (0) ppmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd (0) ppmlb status ( note 5 ) 5 555 aa 2aa 55 555 60 pl 48 pl rd (0) spmlb program (notes 5 , 6 , 12 ) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd (0) spmlb status ( note 5 ) 5 555 aa 2aa 55 555 60 sl 48 sl rd (0)
56 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information pwa = password address. a1:a0 selects portion of password. pwd = password data being verified. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits am ax:a12 uniquely se lect any sector. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycl es. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits ar e 555 or 2aah as shown in tabl e, address bits higher than a11 (except where ba is requ ired) and data bits higher than dq7 are don?t cares. 5. the reset command returns device to reading array. 6. cycle 4 programs the addressed locking bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10. the password is written over four consecutive cycles, at addresses 0-3. 11. a 2 s timeout is required between any two portions of password. 12. a 100 s timeout is requir ed between cy cles 4 and 5. 13. a 1.2 ms timeout is requir ed between cycles 4 and 5. 14. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued and verified again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15. dq1 = 1 if ppb locked, 0 if unlocked. write operation status the device provides several bits to determine the status of a program or erase opera - tion: dq2, dq3, dq5, dq6, and dq7. ta b l e 14 and the following subsections describe the function of these bits. dq7 and dq6 ea ch offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in prog ress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded pro - gram or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is vali d after the rising edge of th e final we# pulse in the com - mand sequence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 st atus also applies to programming during erase suspend. when the embedded program algorithm is complete, the device out - puts the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode.
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 57 advance information during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is comp lete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status in - formation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is ac tive for approximately 400 s, then the bank returns to the read mode. if not al l selected sectors are protected, the em - bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has change d from the complement to true data, it can read valid data at dq15?dq0 on the following read cycles. just prior to the completion of an embedded program or erase operation, dq7 may change asyn - chronously with dq15?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing stat us information to valid data on dq7. depending on when the system samples th e dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 appears on successive read cycles. ta b l e 14 shows the outputs for data# polling on dq7. 6 shows the data# polling algorithm. figure 18 in ac characteristics shows the data# polling timing diagram.
58 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information ry / by # : r ead y / bu sy # the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the stan dby mode, or one of the banks is in the erase-suspend-read mode. ta b l e 14 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being er ased. during chip eras e, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5. figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 59 advance information during an embedded program or erase algorithm operation, successive read cy - cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the op eration is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 400 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo - rithm erases the unprotected sectors, an d ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac - tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in prog ress), dq6 toggles. when the device en - ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter - natively, the system can use dq7 (see ?dq7: data# polling? on page 56 ). if a program address falls within a protected sector, dq6 toggles for approxi - mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-su spend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 14 shows the outputs for toggle bit i on dq6. figure 7 shows the toggle bit algorithm. figure 19 in ?read operation timings? shows the toggle bit timing di - agrams. figure 20 shows the differences between dq2 and dq6 in graphical form. see also ? dq2: toggle bit ii ?. figure 7. to g g l e b i t a l g o r i t h m start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va
60 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information dq2: toggle bit ii the ?toggle bit ii? on dq2, when used wi th dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at a ddresses within those sectors that have been selected for erasure. (the system may use either oe# or ce1# / ce2# to control the read cycles.) but dq2 cannot di stinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. see ta b l e 14 to compare outputs for dq2 and dq6. figure 7 shows the toggle bit algorith m in flowchart form, and the ?dq2: toggle bit ii? explains the algorithm. see also ? dq6: toggle bit i .? figure 19 shows the toggle bit timing diagram. figure 20 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7 for the following discussion. wh enever the system initially be - gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling . typically, the system would note and store the value of the toggle bit after th e first read. after the second read, the system would compare the new value of the toggle bit with the fi rst. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycl es, the system determines that the toggle bit is still toggling, the system also shou ld note whether the value of dq5 is high (see ?dq5: exceeded timing limits? ). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggl e bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operat ion successfully, and the system must write the reset command to re turn to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de - scribed in the previous paragraph. altern atively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo - rithm when it returns to determine th e status of the operation (top of figure 7 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified inter - nal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can note: the system should recheck the toggle bi t even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see ?dq6: toggle bit i? and ?dq2: tog - gle bit ii? for more information. figure 7. toggle bit algorithm
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 61 advance information change a ?0? back to a ?1.? under this condition, the device halts the opera - tion, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspen d-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command se quence, the system may read dq3 to de - termine whether or not erasure has begu n. (the sector erase timer does not apply to the chip erase comm and.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? see also ?sector erase command sequence? on page 49 . after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further comma nds (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device accepts additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last com - mand might not have been accepted. ta b l e 14 shows the status of dq3 relative to the other status bits. notes: 1. dq5 switches to ?1? when an embedded program or em bedded erase operation has ex ceeded the maximum timing limits. ?dq5: exceeded timing limits? for more information. 2. dq7 and dq2 require a valid address wh en reading status information. refe r to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs arra y data if the system addresses a non-busy bank. ta b l e 1 4 . write operation status status dq7 ( note 2 ) dq6 dq5 ( note 1 ) dq3 dq2 ( note 2 ) ry / b y # standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 to g g l e 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a to g g l e 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
62 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground v cc ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe# , and reset# ( note 2 ) . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +13.0 v wp#/acc ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current ( note 3 ) . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8 . maximum dc input voltage on pin a9, oe#, and reset# is +12.5 v whic h may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorte d to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?abs olute maximum ratings? may cause perma- nent damage to the device. this is a stre ss rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute max- imum rating conditions fo r extended periods may affect device reliability. figure 8. maximum overshoot waveforms 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v maximum negative overshoot waveform maximum positive overshoot waveform
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 63 advance information operating ranges operating ranges define those limits be tween which the functionality of the de - vice is guaranteed. industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . ?55c to +125c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7?3.6 v v io or 2.7?3.6 v notes: for all ac and dc specifications, v io = v cc ; contact your local sales office for other v io options.
64 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information dc characteristics notes: 1. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v ccmax . 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 1 m a. 5. not 100% tested. 6. in s29pl129j there are two ce# (ce1#, ce2#). 7. valid ce1#/ce2# conditions: (ce1# = v il, ce2# = v ih, ) or (ce1# = v ih, ce2# = v il ) or (ce1# = v ih, ce2# = v ih ) ta b l e 1 5 . cmos compatible parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current v cc = v cc max ; v id = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; v id = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1 , 2 ) oe# = v ih , v cc = v cc max (note 1) 5 mhz 20 30 ma 10 mhz 45 55 i cc2 v cc active write current (notes 2 , 3 ) oe# = v ih , we# = v il 15 25 ma i cc3 v cc standby current ( note 2 ) ce#, reset#, wp#/acc = v io 0.3 v 0.2 5 a i cc4 v cc reset current ( note 2 ) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v io 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current (notes 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc7 v cc active read-while-erase current (notes 1 , 2 ) oe# = v ih , 5 mhz 21 45 ma 10 mhz 46 70 i cc8 v cc active program-while-erase- suspended current (notes 2 , 5 ) oe# = v ih 17 25 ma i cc9 v cc active page read current ( note 2 ) oe# = v ih , 8 word page read 10 15 ma v il input low voltage v io = 2.7?3.6 v ?0.5 0.8 v v ih input high voltage v io = 2.7?3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 0.4 v v oh output high voltage i oh = ?2.0 ma, v cc = v cc min , v io = 2.7?3.6 v 2.4 v v lko low v cc lock-out voltage ( note 5 ) 2.3 2.5 v
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 65 advance information ac characteristics test conditions switching waveforms note: diodes are in3064 or equivalent figure 9. test setups ta b l e 1 6 . test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times v io = 3.0 v 5 ns input pulse levels v io = 3.0 v 0.0?3.0 v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v ta b l e 1 7 . key to switching waveforms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 2.7 k ? c l 6.2 k ? 3.6 v device under te s t v io = 3.0 v
66 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information vcc ramprate all dc characteristics are specified for a v cc ramp rate > 1v/100 s and v cc >=v ccq - 100 mv. if the v cc ramp rate is < 1v/100 s, a hardware reset required.+ read operations notes: 1. not 100% tested. 2. see figure 9 and table 16 for test specifications 3. measurements performed by placing a 50 ohm te rmination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 4. s29pl129j has two ce# (ce1#, ce2#). 5. valid ce1# / ce2# conditions: (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) or (ce1# = v ih, ce2# = v ih ) 6. valid ce1# / ce2# transitions: (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) to (ce1# = ce2# = v ih ) 7. valid ce1# / ce2# transitions: (ce1# = ce2# = v ih ) to (ce1# = v il ,ce2# = v ih ) or (ce1# = v ih ,ce2# = v il ) 8. for 70pf output load capacitanc e, 2 ns is added to the above t acc ,t ce ,t pacc ,t oe values for all speed grades figure 10. input waveforms and measurement levels ta b l e 1 8 . read-only operations parameter description te s t s e t u p speed options jedec std. 55 60 65 70 unit t avav t rc read cycle time ( note 1 ) min 55 60 65 70 ns t avqv t acc address to output delay ce#, oe# = v il max 55 60 65 70 ns t elqv t ce chip enable to output delay oe# = v il max 55 60 65 70 ns t pacc page access time max 20 25 25 30 ns t glqv t oe output enable to output delay max 20 25 30 ns t ehqz t df chip enable to output high z ( note 3 ) max 16 ns t ghqz t df output enable to output high z (notes 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first ( note 3 ) min 5 ns t oeh output enable hold time ( note 1 ) read min 0 ns toggle and data# polling min 10 ns vio 0.0 v vio/2 vio/2 output measurement level in
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 67 advance information notes: 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 11. read operation timings notes: 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 12. page read operation timings t oh t ce data we# addresses ce# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df amax - a3 ce# oe# a2 - a0 data same page aa ab ac ad qa qb qc qd t acc t pacc t pacc t pacc
68 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information reset note: not 100% tested. ta b l e 1 9 . hardware reset (reset#) parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns notes: 1. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 2. s29pl129j - there are two ce# (ce1#, ce2#). in the below waveform ce# = ce1# or ce2# figure 13. reset timings reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 69 advance information erase/program operations notes: 1. not 100% tested. 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). 4. see table 25, ?erase and pr ogramming performance,? on page 78 for more information. ta b l e 2 0 . erase and program operations parameter speed options jedec std description 55 60 65 70 unit t avav t wc write cycle time ( note 1 ) min 55 60 65 70 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 30 35 ns t aht address hold time from ce1#, ce#2 or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 25 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce1# or ce#2 setup time min 0 ns t wheh t ch ce1# or ce#2 hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 20 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation ( note 4 ) typ 6 s t whwh1 t whwh1 accelerated programming operation ( note 4 ) typ 4 s t whwh2 t whwh2 sector erase operation ( note 4 ) typ 0.5 sec t vcs v cc setup time ( note 1 ) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns min 35 ns
70 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information timing diagrams notes: 1. pa = program address, pd = program data, d out is the true data at the program address 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 14. program operation timings figure 15. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 71 advance information notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status? on page 56 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 16. chip/sector erase operation timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy
72 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information figure 17. back-to-back read/write cycle timings note: va = valid address. illustration shows fi rst status cycle after command sequence , last status read cycle, and array data read cycle figure 18. data# polling timings (during embedded algorithms) oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 73 advance information notes: 1. va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 19. toggle bit timings (during embedded algorithms) note: note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 20. dq2 vs. dq6 oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
74 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information protect/unprotect note: not 100% tested. ta b l e 2 1 . temporary sector unprotect parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s figure 21. temporary sector unprotect timing diagram reset# t vidr v id v il or v ih v id v il or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 75 advance information notes: 1. for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 2. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 3. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# figure 22. sector/sector block protect a nd unprotect timing diagram sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih
76 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information controlled erase operations notes: 1. not 100% tested. 2. see the table 25, ?erase and programming performance,? on page 78 for more information. table 22. alternate ce# controlled er ase and program operations parameter speed options jedec std description 55 60 65 70 unit t avav t wc write cycle time ( note 1 ) min 55 60 65 70 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 30 35 ns t dveh t ds data setup time min 25 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce1# or ce#2 pulse width min 35 40 ns t ehel t cph ce1# or ce#2 pulse width high min 20 25 ns t whwh1 t whwh1 programming operation ( note 2 ) typ 6 s t whwh1 t whwh1 accelerated programming operation ( note 2 ) typ 4 s t whwh2 t whwh2 sector erase operation ( note 2 ) typ 0.5 sec
june 4, 2004 s29pl129j_mcp_00_a0 s29pl129j for mcp 77 advance information notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of th e data written to the device. d out is the data wri tten to the device 4. s29pl129j - during ce1# transitions, ce2# = v ih ; during ce2# transitions, ce1# = v ih 5. s29pl129j - there are two ce# (ce1#, ce2#). in the above waveform ce# = ce1# or ce2# ta b l e 2 3 . alternate ce# controlled write (erase/program) operation timings ta b l e 2 4 . ce1#/ce2# timing parameter description all speed options unit jedec std t ccr ce1#/ce2# recover time min 30 ns t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
78 s29pl129j for mcp s29pl129j_mcp_00_a0 june 4, 2004 advance information notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pa ttern. all values are subject to change. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. all values are subject to change. 3. the typical chip programming time is considerably less th an the maximum chip programmi ng time listed, since most bytes program faster than th e maximum program times listed. 4. in the pre-programming step of the embedded erase al gorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execut e the two- or four-bus-cycle sequence for the program command. see table 12 for further information on command definitions. 6. the device has a minimum erase and prog ram cycle endurance of 100,000 cycles. bga pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. figure 23. timing diagram for alternating between ce1# and ce2# control ta b l e 2 5 . erase and programming performance parameter ty p ( note 1 ) max ( note 2 ) unit comments sector erase time 0.5 2 sec excludes 00h programming prior to erasure ( note 4 ) chip erase time pl129j 135 216 sec word program time 6 100 s excludes system level overhead ( note 5 ) accelerated word program time 4 60 s chip program time ( note 3 ) pl129j 50.4 200 sec parameter symbol parameter description te s t s e t u p ty p max unit c in input capacitance v in = 0 6.3 7 pf c out output capacitance v out = 0 7.0 8 pf c in2 control pin capacitance v in = 0 5.5 8 pf c in3 wp#/acc pin capacitance v in = 0 11 12 pf ce1# t ccr t ccr ce2#
ocotober 16, 2004 psram_type06_14_a1 psram type 6 79 advance information psram type 6 2m word by 16-bit cmos pseu do static ram (32m density) 4m word by 16-bit cmos pse udo static ram (64m density) features ? single power supply voltage of 2.6 to 3.3 v ? direct ttl compatibility for all inputs and outputs ? deep power-down mode: memory cell data invalid ? page operation mode: ? page read operation by 8 words ? logic compatible with sram r/w pin ? standby current ? standby = 70 a (32m) ? standby = 100 a (64m) ? deep power-down standby = 5 a ? access times pin description 32m 64m access time 70 ns ce1# access time 70 ns oe# access time 25 ns page access time 30 ns pin name description a 0 to a 21 address inputs a0 to a2 page address inputs i/o1 to i/o16 data inputs/outputs ce1# chip enable input ce2 chip select input we# write enable input oe# output enable input lb#,ub# data byte control inputs v dd power supply gnd ground nc not connection
80 psram type 6 psram_type06_14_a1 ocotober 16, 2004 advance information functional description legend: l = low-level input (v il ), h = high-level input (v ih ), x = v il or v ih , high-z = high impedance. absolute maximum ratings note: esd immunity: spansion flash memory multi-chip products (mcps) may contain component devices that are developed by spansion and component devices that are develo ped by a third party (third-party components). spansion components are tested and guaranteed to the esd immunity levels listed in the corresponding spansion flash memory qualification database. third-party components are neither tested nor guaranteed by spansion for esd immunity. how - ever, esd test results for third-party components may be available from the component manufacturer. component man - ufacturer contact information is listed in the spansion mc p qualification report, when available. the spansion flash memory qualification database and span sion mcp qualification report are available from spansion sales offices. dc recommended operating conditi ons (ta = -40c to 85c) note: v ih (max) v dd = 1.0 v with 10 ns pulse width. v il (min) -1.0 v with 10 ns pulse width. mode ce1# ce2 oe# we# lb# ub# address i/o 1-8 i/o 9-16 power read (word) l h l h l l x d out d out i ddo read (lower byte) l h l h l h x d out high-z i ddo read (upper byte) l h l h h l x high-z d out i ddo write (word) l h x l l l x d in d in i ddo write (lower byte) l h x l l h x d in invalid i ddo write (upper byte) l h x l h l x invalid d in i ddo outputs disabled l h h h x x x high-z high-z i ddo standby h h x x x x x high-z high-z i ddo deep power-down standby h l x x x x x high-z high-z i ddsd symbol rating value unit v dd power supply voltage -1.0 to 3.6 v v in input voltage -1.0 to 3.6 v v out output voltage -1.0 to 3.6 v t opr operating temperature -40 to 85 c t strg storage temperature -55 to 150 c p d power dissipation 0.6 w i out short circuit output current 50 ma symbol parameter min ty p max unit v dd power supply voltage 2.6 2.75 3.3 v v ih input high voltage 2.0 ? v dd + 0.3 (note) v il input low voltage -0.3 (note) ? 0.4
ocotober 16, 2004 psram_type06_14_a1 psram type 6 81 advance information dc characteristics (ta = -40c to 85c, vdd = 2.6 to 3.3 v) (see note 3 to 4) capacitance (ta = 25c, f = 1 mhz) note: this parameter is sampled periodically and is not 100% tested. ac characteristics and operating conditions (ta = -40c to 85c, vdd = 2.6 to 3.3 v) (see note 5 to 11) symbol parameter test condition min ty p . max unit i il input leakage current v in = 0 v to v dd -1.0 ? +1.0 a i lo output leakage current output disable, v out = 0 v to v dd -1.0 ? +1.0 a v oh output high voltage i oh = - 0.5 ma 2.0 ? v v v ol output low voltage i ol = 1.0 ma ? ? 0.4 v i ddo1 operating current ce1#= v il , ce2 = v ih , i out = 0 ma, t rc = min. et5uz8a-43ds ? ? 40 ma et5vb5a-43ds ? ? 50 i ddo2 page access operating current ce1#= v il , ce2 = v ih , i out = 0 ma page add. cycling, t rc = min. ? ? 25 ma i dds standby current (mos) ce1# = v dd - 0.2 v, ce2 = v dd - 0.2 v et5uz8a-43ds ? ? 70 ma et5vb5a-43ds ? ? 100 a i ddsd deep power-down standby current ce2 = 0.2 v ? ? 5 a symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf symbol parameter min max unit t rc read cycle time 70 10000 ns t acc address access time ? 70 ns t co chip enable (ce1#) access time ? 70 ns t oe output enable access time ? 25 ns t ba data byte control access time ? 25 ns t coe chip enable low to output active 10 ? ns t oee output enable low to output active 0 ? ns t be data byte control low to output active 0 ? ns t od chip enable high to output high-z ? 20 ns t odo output enable high to output high-z ? 20 ns t bd data byte control high to output high-z ? 20 ns
82 psram type 6 psram_type06_14_a1 ocotober 16, 2004 advance information ac test conditions t oh output data hold time 10 ? ns t pm page mode time 70 10000 ns t pc page mode cycle time 30 ? ns t aa page mode address access time ? 30 ns t aoh page mode output data hold time 10 ? ns t wc write cycle time 70 10000 ns t wp write pulse width 50 ? ns t cw chip enable to end of write 70 ? ns t bw data byte control to end of write 60 ? ns t aw address valid to end of write 60 ? ns t as address set-up time 0 ? ns t wr write recovery time 0 ? ns t ceh chip enable high pulse width 10 ? ns t weh write enable high pulse width 6 ? ns t odw we# low to output high-z ? 20 ns t oew we# high to output active 0 ns t ds data set-up time 30 ? ns t dh data hold time 0 ? ns t cs ce2 set-up time 0 ? ns t ch ce2 hold time 300 ? s t dpd ce2 pulse width 10 ? ms t chc ce2 hold from ce1# 0 ? ns t chp ce2 hold from power on 30 ? s parameter condition output load 30 pf + 1 ttl gate input pulse level v dd - 0.2 v, 0.2 v timing measurements v dd x 0.5 reference level v dd x 0.5 t r , t f 5 ns symbol parameter min max unit
ocotober 16, 2004 psram_type06_14_a1 psram type 6 83 advance information timing diagrams read timings figure 24. read cycle t acc t od t oh valid data out t oe t be t oee t bd hi-z hi-z t co fix-h t ba t coe indeterminate t odo t rc address a0 to a20(32m) a0 to a21(64m) ce1# ce2 oe# we# ub# , lb# d out i/o1 to i/o16
84 psram type 6 psram_type06_14_a1 ocotober 16, 2004 advance information figure 25. page read cycle (8 words access) t pm t pc t rc t aoh fix-h hi-z hi-z t be d out t acc t coe t co t oe t ba t oee t pc t aoh t pc d out t od t oh t bd t odo t aa * maximum 8 words d out t aoh d out t aa t aa address a0 to a2 address a 3 to a20(32m) a3 to a21(64m) ce1# ce2 oe# we# ub#, lb# d out i/o1 to i/o16
ocotober 16, 2004 psram_type06_14_a1 psram type 6 85 advance information write timings figure 26. write cycle #1 (we# co ntrolled) (see note 8) ub# d in i/o1 to i/o16 d out i/o1 to i/o16 ce2 ce1# we# address a 0 to a20 a 0 to (32m) a21(64m) t wc t as t bw t wr valid data in t odw t wp t ds t dh t oew (see note 11) (s ) ee note 10 hi-z t cw t wr t weh t aw t wr t ch (see note 9) (see note 9) , lb#
86 psram type 6 psram_type06_14_a1 ocotober 16, 2004 advance information deep power-down timing power-on timing figure 27. write cycle #2 (ce# controlled) (see note 8) figure 28. deep power down timing figure 29. power-on timing t wc t wp t as t cw t wr valid data in t odw t ds t dh t coe hi-z hi-z t aw t wr t ceh t bw t be t wr t ch (see note 9) address a0 to a20 a0 to (32m) a21(64m) we# ce1# ce2 ub#, lb# d out i/o1 to i/o16 d in i/o1 to i/o16 t cs t dpd t ch ce1# ce2 t chc t chp t ch v dd min v dd ce1# ce2
ocotober 16, 2004 psram_type06_14_a1 psram type 6 87 advance information provisions of address skew read in case multiple invalid address cycles shorter than t rc min. sustain over 10 s in an active status, at least one valid address cycle over t rc min. is required dur - ing 10s. write in case multiple invalid address cycles shorter than t wc min. sustain over 10 s in an active status, at least one valid address cycle over t wc min. is required dur - ing 10 s. notes: 1. stresses greater than listed under " absolute maximum ratings " section may cause permanent damage to the device. 2. all voltages are reference to gnd. 3. i ddo depends on the cycle time. 4. i ddo depends on output loading. specified values are defined with the output open condition. 5. ac measurements are assumed t r , t f = 5 ns. 6. parameters t od , t odo , t bd and t od w define the time at which the output goes the open condition and are not output voltage reference levels. 7. data cannot be retained at deep power-down stand-by mode. 8. if oe# is high during the write cycle, the outputs will remain at high impedance. 9. during the output state of i/o signals, input signals of reverse polarity must not be applied. 10. if ce1# or lb#/ub# goes low coincident with or after we# goes low, the outputs w ill remain at high impedance. 11. if ce1# or lb#/ub# goes high coincident with or before we# goes high, the outputs w ill remain at high impedance. figure 30. read figure 31. write over 10 s t rc min ce1# we# a ddress t wp min t wc min ce1# we# a ddress
88 psram type 1 psram_type01_12_a1 august 30, 2004 advance information psram type 1 4mbit (256k word x 16-bit) 8mbit (512k word x 16-bit) 16mbit (1m word x 16-bit) 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) functional description absolute maximum ratings mode ce# ce2/zz# oe# we# ub# lb# addresses i/o 1-8 i/o 9-16 power read (word) l h l h l l x dout dout i active read (lower byte) l h l h h l x dout high-z i active read (upper byte) l h l h l h x high-z dout i active write (word) l h x l l l x din din i active write (lower byte) l h x l h l x din invalid i active write (upper byte) l h x l l h x invalid din i active outputs disabled l h h h x x x high-z high-z i active standby h h x x x x x high-z high-z i standby deep power down h l x x x x x high-z high-z i deep sleep item symbol ratings units voltage on any pin relative to v ss vin, vout -0.2 to v cc +0.3 v voltage on v cc relative to v ss v cc -0.2 to 3.6 v power dissipation p d 1 w storage temperature t stg -55 to 150 c operating temperature t a -25 to 85 c
august 30, 2004 psram_type01_12_a1 psram type 1 89 advance information dc characteristics (4mb psram asynchronous) asynchronous performance grade -70 density 4mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.3 v v il input low level -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v 70 a v cc = 3.3 v i deep sleep deep power down current xa i par 1/4 1/4 array par current xa i par 1/2 1/2 array par current xa
90 psram type 1 psram_type01_12_a1 august 30, 2004 advance information dc characteristics (8mb psram asynchronous) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.6 v 2.7 3.3 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v 0.8 v cc +0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v -0.3 0.4 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a 0.5 a v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 vv i oh = -0.2 ma 0.8 v ccq i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 vv i ol = 0.2 ma 0.2 i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 23 ma 25 ma i standby standby current v cc = 3.0 v 60 a 60 a 70 a v cc = 3.3 v i deep sleep deep power down current xa xa xa i par 1/4 1/4 array par current xa xa xa i par 1/2 1/2 array par current xa xa xa
august 30, 2004 psram_type01_12_a1 psram type 1 91 advance information dc characteristics (16mb psram asynchronous) asynchronous performance grade -55 -70 density 16mb psram 16mb psram symbol parameter conditions minimum maximum units minimum maximum units v cc power supply 2.7 3.6 v 2.7 3.6 v v ih input high level 2.2 v cc + 0.3 v 2.2 v cc + 0.3 v v il input low level -0.3 0.6 v -0.3 0.6 v i il input leakage current vin = 0 to v cc 0.5 a 0.5 a i lo output leakage current oe = v ih or chip disabled 0.5 a 0.5 a v oh output high voltage i oh = -1.0 ma v cc -0.4 v v cc -0.4 v i oh = -0.2 ma i oh = -0.5 ma v ol output low voltage i ol = 2.0 ma 0.4 v 0.4 v i ol = 0.2 ma i ol = 0.5 ma i active operating current v cc = 3.3 v 25 ma 25 ma i standby standby current v cc = 3.0 v 100 a 100 a v cc = 3.3 v i deep sleep deep power down current x a x a i par 1/4 1/4 array par current x a x a i par 1/2 1/2 array par current x a x a
92 psram type 1 psram_type01_12_a1 august 30, 2004 advance information dc characteristics (16mb psram page mode) page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram symbol parameter conditions min max units min max units min max units v cc power supply 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v -0.2 0.2 vccq v -0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 1a 1a 1a i lo output leakage current oe = v ih or chip disabled 1a 1a 1a v oh output high voltage i oh = -1.0 ma vv v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a v cc = 3.3 v 100 100 100 i deep sleep deep power down current 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 65 a 65 a i par 1/2 1/2 array par current 80 a 80 a 80 a
august 30, 2004 psram_type01_12_a1 psram type 1 93 advance information dc characteristics (32mb psram page mode) page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram symbol parameter conditions min max units min max units min max units min max units v cc power supply 2.7 3.6 v 2.7 3.3 v 2.7 3.3 v 2.7 3.3 v v ih input high level 1.4 v cc + 0.2 v0.8 vccq v cc + 0.2 v0.8 vccq v cc + 0.2 v 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.4 v -0.2 0.2 vccq v-0.2 0.2 vccq v-0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 0.5 a 1 a 1 a 1 a i lo output leakage current oe = v ih or chip disabled 0.5 a 1 a 1 a 1 a v oh output high voltage i oh = -1.0 ma vv vv i oh = -0.2 ma 0.8 vccq i oh = -0.5 ma 0.8 vccq 0.8 vccq 0.8 vccq v ol output low voltage i ol = 2.0 ma vv vv i ol = 0.2 ma 0.2 i ol = 0.5 ma 0.2 vccq 0.2 vccq 0.2 vccq i active operating current v cc = 3.3 v 25 ma 25 ma 25 ma 25 ma i standby standby current v cc = 3.0 v a a a a v cc = 3.3 v 100 120 120 120 i deep sleep deep power down current 10 a 10 a 10 a 10 a i par 1/4 1/4 array par current 65 a 75 a 75 a 75 a i par 1/2 1/2 array par current 80 a 90 a 90 a 90 a
94 psram type 1 psram_type01_12_a1 august 30, 2004 advance information dc characteristics (64mb psram page mode) timing test conditions page mode performance grade -70 density 64mb psram symbol parameter conditions min max units v cc power supply 2.7 3.3 v v ih input high level 0.8 vccq v cc + 0.2 v v il input low level -0.2 0.2 vccq v i il input leakage current vin = 0 to v cc 1a i lo output leakage current oe = v ih or chip disabled 1a v oh output high voltage i oh = -1.0 ma v i oh = -0.2 ma i oh = -0.5 ma 0.8 vccq v ol output low voltage i ol = 2.0 ma v i ol = 0.2 ma i ol = 0.5 ma 0.2 vccq i active operating current v cc = 3.3 v 25 ma i standby standby current v cc = 3.0 v a v cc = 3.3 v 120 i deep sleep deep power down current 10 a i par 1/4 1/4 array par current 65 a i par 1/2 1/2 array par current 80 a item input pulse level 0.1 v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc operating temperature -25c to +85c
august 30, 2004 psram_type01_12_a1 psram type 1 95 advance information output load circuit power up sequence after applying power, maintain a stable power supply for a minimum of 200 s after ce# > v ih . figure 32. output load circuit v cc 30 pf i/o 14.5k 14.5k output load
96 psram type 1 psram_type01_12_a1 august 30, 2004 advance information ac characteristics (4mb psram page mode) asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units read trc read cycle time 70 ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 20 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 020ns tbhz ub#, lb# disable to high-z output 020ns tohz output disable to high-z output 020ns toh output hold from address change 10 ns
august 30, 2004 psram_type01_12_a1 psram type 1 97 advance information write twc write cycle time 70 ns tcw chipselect to end of write 70 ns tas address set up time 0ns taw address valid to end of write 70 ns tbw ub#, lb# valid to end of write 70 ns twp write pulse width 55 ns twr write recovery time 0ns twhz write to output high-z 20 ns tdw data to write time overlap 25 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns other tpc page read cycle x tpa page address access time x twpc page write cycle x tcp chip select high pulse width x asynchronous performance grade -70 density 4mb psram 3 volt symbol parameter min max units
98 psram type 1 psram_type01_12_a1 august 30, 2004 advance information ac characteristics (8mb psram asynchronous) asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 55 ns 70 ns 70 ns taa address access time 55 ns 70 ns 70 ns tco chip select to output 55 ns 70 ns 70 ns toe output enable to valid output 30 ns 35 ns 20 ns tba ub#, lb# access time 55 ns 70 ns 70 ns tlz chip select to low-z output 5 ns 5 ns 10 ns tblz ub#, lb# enable to low-z output 5 ns 5 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 020ns025ns 020ns tbhz ub#, lb# disable to high-z output 020ns025ns 020ns tohz output disable to high-z output 020ns025ns 020ns toh output hold from address change 10 ns 10 ns 10 ns
august 30, 2004 psram_type01_12_a1 psram type 1 99 advance information write twc write cycle time 55 ns 70 ns 70 ns tcw chip select to end of write 45 ns 55 ns 70 ns tas address set up time 0ns0ns0ns taw address valid to end of write 45 ns 55 ns 70 ns tbw ub#, lb# valid to end of write 45 ns 55 ns 70 ns twp write pulse width 45 ns 55 ns 55 ns twr write recovery time 0ns0ns0ns twhz write to output high-z 25 ns 25 20 ns tdw data to write time overlap 40 ns 40 ns 25 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width xxnsxxnsxxns other tpc page read cycle x x x tpa page address access time xxx twpc page write cycle x x x tcp chip select high pulse width xxx asynchronous version b c performance grade -55 -70 -70 density 8mb psram 8mb psram 8mb psram 3 volt symbol parameter min max units min max units min max units
100 psram type 1 psram_type01_12_a1 august 30, 2004 advance information ac characteristics (16mb psram asynchronous) asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units read trc read cycle time 55 ns 70 ns taa address access time 55 ns 70 ns tco chip select to output 55 ns 70 ns toe output enable to valid output 30 ns 35 ns tba ub#, lb# access time 55 ns 70 ns tlz chip select to low-z output 5ns5ns tblz ub#, lb# enable to low-z output 5ns5ns tolz output enable to low-z output 5ns5ns thz chip enable to high-z output 025ns025ns tbhz ub#, lb# disable to high-z output 025ns025ns tohz output disable to high-z output 025ns025ns toh output hold from address change 10 ns 10 ns
august 30, 2004 psram_type01_12_a1 psram type 1 101 advance information write twc write cycle time 55 ns 70 ns tcw chipselect to end of write 50 ns 55 ns tas address set up time 0ns0ns taw address valid to end of write 50 ns 55 ns tbw ub#, lb# valid to end of write 50 ns 55 ns twp write pulse width 50 ns 55 ns twr write recovery time 0ns0ns twhz write to output high-z 25 ns 25 ns tdw data to write time overlap 25 ns 25 ns tdh data hold from write time 0ns0ns tow end write to output low-z 55 tow write high pulse width xxnsxxns other tpc page read cycle x x tpa page address access time xx twpc page write cycle x x tcp chip select high pulse width xx asynchronous performance grade -55 -70 density 16mb psram 16mb psram 3 volt symbol parameter min max units min max units
102 psram type 1 psram_type01_12_a1 august 30, 2004 advance information ac characteristics (16mb psram page mode) page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units read trc read cycle time 60 20k ns 65 20k ns 70 20k ns taa address access time 60 ns 65 ns 70 ns tco chip select to output 60 ns 65 ns 70 ns toe output enable to valid output 25 ns 25 ns 25 ns tba ub#, lb# access time 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns tolz output enable to low-z output 5ns5ns5ns thz chip enable to high-z output 05ns05ns05ns tbhz ub#, lb# disable to high-z output 05ns05ns05ns tohz output disable to high-z output 05ns05ns05ns toh output hold from address change 5ns5ns5ns
august 30, 2004 psram_type01_12_a1 psram type 1 103 advance information write twc write cycle time 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 50 ns 60 ns 60 ns tas address set up time 0ns0ns0ns taw address valid to end of write 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 50 ns 60 ns 60 ns twp write pulse width 50 ns 50 ns 50 ns twr write recovery time 0ns0ns0ns twhz write to output high-z 5ns 5ns 5ns tdw data to write time overlap 20 ns 20 ns 20 ns tdh data hold from write time 0ns0ns0ns tow end write to output low-z 555 tow write high pulse width 7.5 ns 7.5 ns 7.5 ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns page mode performance grade -60 -65 -70 density 16mb psram 16mb psram 16mb psram 3 volt symbol parameter min max units min max units min max units
104 psram type 1 psram_type01_12_a1 august 30, 2004 advance information ac characteristics (32mb psram page mode) page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units read trc read cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns taa address access time 65 ns 60 ns 65 ns 70 ns tco chip select to output 65 ns 60 ns 65 ns 70 ns toe output enable to valid output 20 ns 25 ns 25 ns 25 ns tba ub#, lb# access time 65 ns 60 ns 65 ns 70 ns tlz chip select to low-z output 10 ns 10 ns 10 ns 10 ns tblz ub#, lb# enable to low-z output 10 ns 10 ns 10 ns 10 ns tolz output enable to low-z output 5 ns 5 ns 5 ns 5 ns thz chip enable to high-z output 020ns 0 5 ns 0 5ns 0 5ns tbhz ub#, lb# disable to high-z output 020ns 0 5 ns 0 5ns 0 5ns tohz output disable to high-z output 020ns 0 5 ns 0 5ns 0 5ns toh output hold from address change 5 ns 5 ns 5 ns 5 ns
august 30, 2004 psram_type01_12_a1 psram type 1 105 advance information write twc write cycle time 65 20k ns 60 20k ns 65 20k ns 70 20k ns tcw chipselect to end of write 55 ns 50 ns 60 ns 60 ns tas address set up time 0 ns 0 ns 0 ns 0 ns taw address valid to end of write 55 ns 50 ns 60 ns 60 ns tbw ub#, lb# valid to end of write 55 ns 50 ns 60 ns 60 ns twp write pulse width 55 20k ns 50 ns 50 ns 50 ns twr write recovery time 0 ns 0 ns 0 ns 0 ns twhz write to output high-z 5 ns 5 ns 5 ns 5 ns tdw data to write time overlap 25 ns 20 ns 20 ns 20 ns tdh data hold from write time 0 ns 0 ns 0 ns 0 ns tow end write to output low-z 55 5 5 tow write high pulse width 7.5 ns 7.5 ns 7.5 ns 7.5 ns other tpc page read cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tpa page address access time 25 ns 25 ns 25 ns 25 ns twpc page write cycle 25 20k ns 25 20k ns 25 20k ns 25 20k ns tcp chip select high pulse width 10 ns 10 ns 10 ns 10 ns page mode version c e performance grade -65 -60 -65 -70 density 32mb psram 32mb psram 32mb psram 32mb psram 3 volt symbol parameter min max units min max units min max units min max units
106 psram type 1 psram_type01_12_a1 august 30, 2004 advance information ac characteristics (64mb psram page mode) page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units read trc read cycle time 70 20k ns taa address access time 70 ns tco chip select to output 70 ns toe output enable to valid output 25 ns tba ub#, lb# access time 70 ns tlz chip select to low-z output 10 ns tblz ub#, lb# enable to low-z output 10 ns tolz output enable to low-z output 5ns thz chip enable to high-z output 05ns tbhz ub#, lb# disable to high-z output 05ns tohz output disable to high-z output 05ns toh output hold from address change 5ns
august 30, 2004 psram_type01_12_a1 psram type 1 107 advance information timing diagrams read cycle write twc write cycle time 70 20k ns tcw chipselect to end of write 60 ns tas address set up time 0ns taw address valid to end of write 60 ns tbw ub#, lb# valid to end of write 60 ns twp write pulse width 50 20k ns twr write recovery time 0ns twhz write to output high-z 5ns tdw data to write time overlap 20 ns tdh data hold from write time 0ns tow end write to output low-z 5 tow write high pulse width 7.5 ns other tpc page read cycle 20 20k ns tpa page address access time 20 ns twpc page write cycle 20 20k ns tcp chip select high pulse width 10 ns figure 33. timing of read cycle (ce# = oe# = v il , we# = zz# = v ih ) page mode performance grade -70 density 64mb psram 3 volt symbol parameter min max units a ddress data out t rc t aa t oh data valid previous data valid
108 psram type 1 psram_type01_12_a1 august 30, 2004 advance information figure 34. timing waveform of read cycle (we# = zz# = v ih ) address lb#, ub# oe# data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t lb, t ub t blz ce#
august 30, 2004 psram_type01_12_a1 psram type 1 109 advance information figure 35. timing waveform of page mode read cycle (we# = zz# = v ih ) page address (a4 - a20) lb#, ub# oe# t aa t co t hz t ohz t bhz t olz t oe high-z data out t lb, t ub t blz, ce# word address (a0 - a3) t pa t rc t pgmax t pc
110 psram type 1 psram_type01_12_a1 august 30, 2004 advance information write cycle figure 36. timing waveform of write cy cle (we# control, zz# = v ih ) figure 37. timing waveform of write cycle (ce# control, zz# = v ih ) addr es s dat a in ce# data valid t wc t aw t cw t wr t whz t dh high-z we# da ta out high-z t ow t as t wp t dw t bw lb#, ub# ad dr es s we# data valid t wc t aw t cw t wr t dh lb#, ub# dat a in high-z t as t wp t dw t bw da ta o ut t whz ce#
august 30, 2004 psram_type01_12_a1 psram type 1 111 advance information power savings modes (for 16m page mode, 32m and 64m only) there are several power savings modes. ? partial array self refresh ? temperature compensated refresh (64m) ? deep sleep mode ? reduced memory size (32m, 16m) the operation of the power saving modes ins controlled by the settings of bits contained in the mode register. this defini tion of the mode register is shown in figure 39 and the various bits are used to enable and disable the various low power modes as well as enabling page mo de operation. the mode register is set by using the timings defined in figure xxx. partial array self refresh (par) in this mode of operation, the internal refresh operation can be restricted to a 16mb, 32mb, or 48mb portion of the array. the array partition to be refreshed is determined by the respective bit settings in the mode register. the register set - tings for the pasr operation are defined in table xxx. in this pasr mode, when zz# is active low, only the portion of th e array that is set in the register is re - figure 38. timing waveform of page mode write cycle (zz# = v ih ) page a ddr es s (a4 - a 20) lb#, ub# we# t wp t cw t dw high-z dat a out t lbw, t ubw ce# wor d a ddr es s (a0 - a3 ) t wc t pwc t dh t pdw t pdh t pdw t pdh t as t pgmax
112 psram type 1 psram_type01_12_a1 august 30, 2004 advance information freshed. the data in the remainder of th e array will be lost. the pasr operation mode is only available during standby ti me (zz# low) and once zz# is returned high, the device resumes full array refresh. all future pasr cycles will use the contents of the mode register that has been previously set. to change the ad - dress space of the pasr mode, the mode register must be reset using the previously defined procedures. for pasr to be activated, the register bit, a4 must be set to a one (1) value, ?pasr enabled?. if this is the case, pasr will be acti - vated 10 s after zz# is brought low. if the a4 register bit is set equal to zero (0), pasr will not be activated. temperature compensated refresh (for 64mb) in this mode of operation, the internal refresh rate can be optimized for the op - eration temperature used and this can then lower standby current. the dram array in the psram must be refreshed inte rnally on a regular basis. at higher temperatures, the dram cell must be re freshed more often than at lower tem - peratures. by setting the temperature of operation in the mode register, this refresh rate can be optimized to yield the lowest standby current at the given op - erating temperature. there are four different temperature settings that can be programmed in to the psram. these are defined in figure 39 . deep sleep mode in this mode of operation, the internal re fresh is turned off and all data integrity of the array is lost. deep sleep is entered by bringing zz# low with the a4 reg - ister bit set to a zero (0), ?deep sleep enabled?. if this is the case, deep sleep will be entered 10 s after zz# is brought low. the device will remain in this mode as long as zz# remains low. if the a4 re gister bit is set equal to one (1), deep sleep will not be activated. reduced memory size (for 32m and 16m) in this mode of operation, the 32mb psram can be operated as a 8mb or 16mb device. the mode and array size are determ ined by the settings in the va register. the va register is set according to the following timings and the bit settings in the table ?address patterns for rms?. the rms mode is enabled at the time of zz transitioning high and the mode remains ac tive until the register is updated. to return to the full 32mb address space, th e va register must be reset using the previously defined procedures. while operating in the rms mode, the unselected portion of the array may not be used. other mode register settings (for 64m) the page mode operation can also be en abled and disabled using the mode reg - ister. register bit a7 controls the operation of page mode and setting this bit to a one (1), enables page mode. if the register bit a7 is set to a zero (0), page mode operation is disabled.
august 30, 2004 psram_type01_12_a1 psram type 1 113 advance information figure 39. mode register figure 40. mode register update timings (ub#, lb#, oe# are don?t care) deep sleep enable/disabl e 0 = deep sleep enabled 1 = deep sleep disabled (default) par section 1 1 1 = top 1/4 array 1 1 0 = top 1/2 array 1 0 1 = top 3/4 array 1 0 0 = no par 0 1 1 = bottom 1/4 array 0 1 0 = bottom 1/2 array 0 0 1 = bottom 3/4 array 0 0 0 = full array (default) reserved must set to all 0 a21 - a8 a7 a6 a5 a4 a3 a2 a1 a0 page mode 0 = page mode disabled (default) 1 = page mode enabled te m p compensated refresh 1 0 = 15 o c 0 1 = 45 o c 0 0 = 70 o c 1 1 = 85 o c (default) array mode for zz# 0 = par (default) 1 = rms 64 mb 32 mb / 16 mb address zz# t wc t as ce# we# t zzwe t aw t wp t wr t cdzz
114 psram type 1 psram_type01_12_a1 august 30, 2004 advance information mode register update and deep sleep timings notes: 1. minimum cycle time for writing register is equal to speed grade of product. figure 41. deep sleep mode - entry/exit timings (for 64m) figure 42. deep sleep mode - entry/exit timings (for 32m and 16m) item symbol min max unit note chip deselect to zz# low t cdzz 5 ns zz# low to we# low t zzwe 10 500 ns write register cycle time t wc 70/85 ns 1 chip enable to end of write t cw 70/85 ns 1 address valid to end of write t aw 70/85 ns 1 write recovery time t wr 0 ns address setup time t as 0 ns write pulse width t wr 40 ns deep sleep pulse width t zzmin 10 s deep sleep recovery t r 200 s zz# t zzmin t cdzz t r ce# a4 zz# t wc t bw t as ce# we# t zzwe t aw t wp t wr t r t zzmin lb#, ub#
august 30, 2004 psram_type01_12_a1 psram type 1 115 advance information address patterns for pasr (a4=1) (64m) a2 a1 a0 active section address space size density 1 1 1 top quarter of die 300000h-3fffffh 1mb x 16 16mb 1 1 0 top half of die 200000h-3fffffh 2mb x 16 32mb 1 0 1 reserved 1 0 0 no pasr none 0 0 0 1 1 bottom quarter of die 000000h-0fffffh 1mb x 16 16mb 0 1 0 bottom half of die 000000h-1fffffh 2mb x 16 32mb 0 0 1 reserved 0 0 0 full array 000000h-3fffffh 4mb x 16 64mb
116 psram type 1 psram_type01_12_a1 august 30, 2004 advance information deep icc characteristics (for 64mb) address patterns for par (a3= 0, a4=1) (32m) address patterns for rms (a3 = 1, a4 = 1) (32m) item symbol te s t array partition ty p max unit pasr mode standby current i pasr v in = v cc or 0v, chip disabled, t a = 85c none 10 a 1/4 array 60 1/2 array 80 full array 120 item symbol max temperature ty p max unit temperature compensated refresh current i tcr 15c 50 a 45c 60 70c 80 85c 120 item symbol te s t ty p max unit deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 25c 10 a a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb x 0 0 full die 000000h - 1fffffh 2mb x 16 32mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 000000h - 07ffffh 512kb x 16 8mb 0 1 0 one-half of die 000000h - 0fffffh 1mb x 16 16mb 1 1 1 one-quarter of die 180000h - 1fffffh 512kb x 16 8mb 1 1 0 one-half of die 100000h - 1fffffh 1mb x 16 16mb
august 30, 2004 psram_type01_12_a1 psram type 1 117 advance information low power icc characteristics (32m) address patterns for par (a3= 0, a4=1) (16m) address patterns for rms (a3 = 1, a4 = 1) (16m) low power icc characteristics (16m) item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 75 a 1/2 array 90 a rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 8mb device 75 a 16mb device 90 a deep sleep current i zz v in = v cc or 0v, chip in zz mode, t a = 85 o c 10 a a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb x 0 0 full die 00000h - fffffh 1mb x 16 16mb 1 1 1 one-quarter of die c0000h - ffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - 1fffffh 512kb x 16 8mb a2 a1 a0 active section address space size density 0 1 1 one-quarter of die 00000h - 0ffffh 256kb x 16 4mb 0 1 0 one-half of die 00000h - 7ffffh 512kb x 16 8mb 1 1 1 one-quarter of die c0000h - fffffh 256kb x 16 4mb 1 1 0 one-half of die 80000h - fffffh 512kb x 16 8mb item symbol te s t array partition ty p max unit par mode standby current i par v in = v cc or 0v, chip disabled, t a = 85 o c 1/4 array 65 a 1/2 array 80 rms mode standby current i rmssb v in = v cc or 0v, chip disabled, t a = 85 o c 4mb device 65 a 8mb device 80 deep sleep current i zz v in = v cc or 0v, chip in zz# mode, t a = 85 o c 10 a
118 type 2 psram psram_type02_15a1 june 25, 2004 advance information ty p e 2 p s r a m 16mbit (1m word x 16-bit) 32mbit (2m word x 16-bit) 64mbit (4m word x 16-bit) 128mbit (8m word x 16-bit) features ? process technology: cmos ? organization: x16 bit ? power supply voltage: 2.7~3.1v ? three state outputs ? compatible with low power sram product information pin description density v cc range standby (isb1, max.) operating (icc2, max.) mode 16mb 2.7-3.1v 80 a 30 ma dual cs 16mb 2.7-3.1v 80 a 35 ma dual cs and page mode 32mb 2.7-3.1v 100 a 35 ma dual cs 32mb 2.7-3.1v 100 a 40 ma dual cs and page mode 64mb 2.7-3.1v tbd tbd dual cs 64mb 2.7-3.1v tbd tbd dual cs and page mode 128mb 2.7-3.1v tbd tbd dual cs and page mode pin name description i/o cs1#, cs2 chip select i oe# output enable i we# write enable i lb#, ub# lower/upper byte enable i a0-a19 (16m) a0-a20 (32m) a0-a21 (64m) a0-a22 (128m) address inputs i i/o0-i/o15 data inputs/outputs i/o v cc /v ccq power supply ? v ss /v ssq ground ? nc not connection ? dnu do not use ?
june 25, 2004 psram_type02_15a1 type 2 psram 119 advance information power up sequence 1. apply power. 2. maintain stable power (v cc min.=2.7v) for a minimum 200 s with cs1#=high or cs2=low. timing diagrams power up notes: 1. after v cc reaches v cc (min.), wait 200 s with cs1# high. then the device gets into the normal operation. notes: 1. after v cc reaches v cc (min.), wait 200 s with cs2 low. then the device gets into the normal operation. figure 43. power up 1 (cs1# controlled) figure 44. power up 2 (cs2 controlled) min. 200 s v cc cs 1# cs2 v cc(min) normal operation power up mode min. 200 s v cc cs1# cs2 v cc(mi n) normal operation power up mode ~ ~ ~ ~ ~ ~ ~ ~
120 type 2 psram psram_type02_15a1 june 25, 2004 advance information functional description legend: x = don?t care (must be low or high state). absolute maximum ratings notes: 1. stresses greater than those listed under " absolute maximum ratings " section may cause permanent damage to the device. functional operation should be restricted to be used un der recommended operating condit ion. exposure to absolute maximum rating conditions longer th an one second may affect reliability. dc recommended operating conditions notes: 1. ta=-40 to 85c, unless otherwise specified. 2. overshoot: v cc +1.0v in case of pulse width 20ns. 3. undershoot: -1.0v in case of pulse width 20ns. 4. overshoot and undershoot ar e sampled, not 100% tested. mode cs1# cs2 oe# we# lb# ub# i/o 1-8 i/o 9-16 power deselected h x x x x x high-z high-z standby deselected x l x x x x high-z high-z standby deselected x x x x h h high-z high-z standby output disabled l h h h l x high-z high-z active outputs disabled l h h h x l high-z high-z active lower byte read l h l h l h d out high-z active upper byte read l h l h h l high-z d out active word read l h l h l l d out d out active lower byte write l h x l l h d in high-z active upper byte write l h x l h l high-z d in active word write l h x l l l d in d in active item symbol ratings unit voltage on any pin relative to v ss v in , v out -0.2 to v cc +0.3v v voltage on v cc supply relative to v ss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c symbol parameter min ty p max unit v cc power supply voltage 2.7 2.9 3.1 v v ss ground 0 0 0 v ih input high voltage 2.2 ? v cc + 0.3 (note 2) v il input low voltage -0.2 (note 3) ? 0.6
june 25, 2004 psram_type02_15a1 type 2 psram 121 advance information capacitance (ta = 25c, f = 1 mhz) note: this parameter is sampled periodically and is not 100% tested. dc and operating characteristics common symbol parameter test condition min max unit c in input capacitance v in = 0v ? 8 pf c io input/output capacitance v out = 0v ? 10 pf item symbol test conditions min ty p max unit input leakage current i li v in =v ss to v cc -1 ? 1 a output leakage current i lo cs1#=v ih or cs2=v il or oe#=v ih or we#=v il or lb#=ub#=v ih , v io =v ss to v cc -1 ? 1 a output low voltage v ol i ol =2.1ma ? ? 0.4 v output high voltage v oh i oh =-1.0ma 2.4 ? ? v
122 type 2 psram psram_type02_15a1 june 25, 2004 advance information 16m psram notes: 1. standby mode is supposed to be set up after at least one ac tive operation after power up. is b1 is measure after 60ms from the time when standby mode is set up. 32m psram notes: 1. standby mode is supposed to be set up after at least one ac tive operation after power up. is b1 is measure after 60ms from the time when standby mode is set up. item symbol test conditions min ty p max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in vcc-0.2v ? ? 7 ma i cc2 async cycle time=min, i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in =v ih or v il ? ? 30 ma page cycle time=t rc +3t pc , i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in -v ih or v il 35 ma standby current (cmos) i sb1 (note 1) other inputs=0-vcc 1. cs1# v cc - 0.2, cs2 v cc - 0.2v (cs1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) ? ? 80 ma item symbol test conditions min ty p max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in vcc-0.2v ? ? 7 ma i cc2 async cycle time=min, i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in =v ih or v il ? ? 35 ma page cycle time=t rc +3t pc , i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in -v ih or v il 40 ma standby current (cmos) i sb1 (note 1) other inputs=0-vcc 1. cs1# v cc - 0.2, cs2 v cc - 0.2v (cs1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) ? ? 100 ma
june 25, 2004 psram_type02_15a1 type 2 psram 123 advance information 64m psram notes: 1. standby mode is supposed to be set up after at least one ac tive operation after power up. is b1 is measure after 60ms from the time when standby mode is set up. 128m psram notes: 1. standby mode is supposed to be set up after at least one active operation after power up. i sb1 is measured after 60ms from the time when standby mode is set up. item symbol test conditions min ty p max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in vcc-0.2v ? ? tbd ma i cc2 async cycle time=min, i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in =v ih or v il ? ? tbd ma page cycle time=t rc +3t pc , i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in -v ih or v il tbd ma standby current (cmos) i sb1 (note 1) other inputs=0-vcc 1. cs1# v cc - 0.2, cs2 v cc - 0.2v (cs1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) ? ? tbd ma item symbol test conditions min ty p max unit average operating current i cc1 cycle time=1s, 100% duty, i io =0ma, cs1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in vcc-0.2v ? ? tbd ma i cc2 cycle time=t rc +3t pc , i io =0ma, 100% duty, cs1#=v il , cs2=v ih lb#=v il and/or ub#=v il , v in -v ih or v il ? ? tbd ma standby current (cmos) i sb1 (note 1) other inputs=0-v cc 1. cs1# v cc - 0.2, cs2 v cc - 0.2v (cs1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) ? ? tbd ma
124 type 2 psram psram_type02_15a1 june 25, 2004 advance information ac operating conditions test conditions (test load and test input/output reference) ? input pulse level: 0.4 to 2.2v ? input rising and falling time: 5ns ? input and output reference voltage: 1.5v ? output load (see figure 45 ): cl=50pf note: including scope and jig capacitance. figure 45. output load c l dout
june 25, 2004 psram_type02_15a1 type 2 psram 125 advance information ac characteristics (ta = -40c to 85c, v cc = 2.7 to 3.1 v) notes: 1. t wp (min)=70ns for continuous write operation over 50 times. symbol parameter speed bins unit 70ns min max read t rc read cycle time 70 ? ns t aa address access time ? 70 ns t co chip select to output ? 70 ns t oe output enable to valid output ? 35 ns t ba ub#, lb# access time ? 70 ns t lz chip select to low-z output 10 ? ns t blz ub#, lb# enable to low-z output 10 ? ns t olz output enable to low-z output 5 ? ns t hz chip disable to high-z output 0 25 ns t bhz ub#, lb# disable to high-z output 0 25 ns t ohz output disable to high-z output 0 25 ns t oh output hold from address change 5 ? ns t pc page cycle time 25 ? ns t pa page access time ? 20 ns write t wc write cycle time 70 ? ns t cw chip select to end of write 60 ? ns t as address set-up time 0 ? ns t aw address valid to end of write 60 ? ns t bw ub#, lb# valid to end of write 60 ? ns t wp write pulse width 55 (note 1) ? ns t wr write recovery time 0 ? ns t whz write to output high-z 0 25 ns t dw data to write time overlap 30 ? ns t dh data hold from write time 0 ? ns t ow end write to output low-z 5 ? ns
126 type 2 psram psram_type02_15a1 june 25, 2004 advance information timing diagrams read timings notes: 1. address controlled, cs1#=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il . notes: 1. we#=v ih . figure 46. timing waveform of read cycle(1) figure 47. timing waveform of read cycle(2) address data out previous data valid data valid t aa t rc t oh data valid high-z t rc t oh t aa t ba t oe t olz t blz t lz t ohz t bhz t hz t co address ub#, lb# oe# data out cs1# cs2
june 25, 2004 psram_type02_15a1 type 2 psram 127 advance information notes: 1. 16mb: a2 ~ a19, 32mb: a2 ~ a20, 64mb: a2 ~ a21, 128mb: a2 ~ a22. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. t oe (max) is met only when oe# becomes enabled after t aa (max). if invalid address signals shorter than min. t rc are continuously repeated for over 4s, the device needs a normal read timing (t rc ) or needs to sustain standby state for min. t rc at least once in every 4s. write timings figure 48. timing waveform of page cycle (page mode only) figure 49. write cycle #1 (we# controlled) data valid data valid data valid data valid valid address valid address valid address valid address valid address t pc t pa high z a1~a0 dq15~dq0 oe# t ohz t oe t co t aa cs1# cs2 address 1) address cs1# data undefined ub#, lb# we# data in data out t wc t cw t wr t aw t bw t wp t as t dh t dw t whz t ow high-z high-z data valid cs2
128 type 2 psram psram_type02_15a1 june 25, 2004 advance information figure 50. write cycle #2 (cs1# controlled) figure 51. timing waveform of write cycle(3) (cs2 controlled) address data valid ub#, lb# we# data in data out high-z t wc t cw t aw t bw t wp t dh t dw t wr t as cs1# cs2 address data valid ub#, lb# we# data in data out high-z t wc t cw t aw t bw t wp(1) t dh t dw t wr t as cs1# cs2
june 25, 2004 psram_type02_15a1 type 2 psram 129 advance information notes: 1. a write occurs du ring the overlap (t wp ) of low cs1# and low we#. a write begins when cs1# goes low and we# goes low with asserting ub# or lb# for single byte operation or simult aneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs1# goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs1# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr is applied in case a write ends with cs1# or we# going high. figure 52. timing waveform of write cycle(4) (ub#, lb# controlled) address data valid ub #, lb# we# data in data out high-z t wc t cw t bw t wp t dh t dw t wr t aw t as cs1# cs2
130 psram type 7 psram_type07_13_a1 november 2, 2004 advance information psram type 7 16mb (1m word x 16-bit) 32mb (2m word x 16-bit) 64mb (4m word x 16-bit) cmos 1m/2m/4m-word x 16-bit fast cyc le random access memory with low power sram interface features ? asynchronous sram interface ? fast access time ? tce = taa = 60ns max (16m) ? tce = taa = 65ns max (32m/64m) ? 8 words page access capability ? tpaa = 20ns max (32m/64m) ? low voltage operating condition ? vdd = +2.7v to +3.1v ? wide operating temperature ? ta = -30c to +85c ? byte control by lb and ub ? various power down modes ?sleep (16m) ? sleep, 4m-bit partial, or 8m-bit partial (32m) ? sleep, 8m-bit partial, or 16m-bit partial (64m) pin description pin name description a 21 to a 0 address input: a 19 to a 0 for 16m, a 20 to a 0 for 32m, a 21 to a 0 for 64m ce1# chip enable (low active) ce2# chip enable (high active) we# write enable (low active) oe# output enable (low active) ub# upper byte control (low active) lb# lower byte control (low active) dq 16 - 9 upper byte data input/output dq 8 - 1 lower byte data input/output v dd power supply v ss ground
november 2, 2004 psram_type07_13_a1 psram type 7 131 advance information functional description legend: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance. notes: 1. should not be kept this logic condition longer than 1 ms. please contact local spansion representative for the relaxation of 1ms limitation. 2. power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of the power-down program, 16m has data retentio n in all modes except power down. refer to power down for details. 3. can be either v il or v ih but must be valid before read or write. power down (for 32m, 64m only) power down the power down is a low-power idle state controlled by ce2. ce2 low drives the device in power-down mode and maintain s the low-power idle state as long as ce2 is kept low. ce2 high resumes th e device from power-down mode. these devices have three power-down modes. these can be programmed by series of read/write operation. each mode has following features. the default state is sleep and it is the lowest power consumpt ion but all data is lost once ce2 is brought to low for power down. it is not required to program to sleep mode after power-up. mode ce2# ce1# we# oe# lb# ub# a 21-0 dq 8-1 dq 16-9 standby (deselect) h h x x x x x high-z high-z output disable (note 1) hl hhxx note 3 high-z high-z output disable (no read) hl h h valid high-z high-z read (upper byte) h l valid high-z output valid read (lower byte) l h valid output valid high-z read (word) l l valid output valid output valid no write lh h h valid invalid invalid write (upper byte) h l valid invalid input valid write (lower byte) l h valid input valid invalid write (word) l l valid input valid input valid power down lxxxxx x high-z high-z 32m 64m mode retention data retention address mode retention data retention address sleep (default) no n/a sleep (default) no n/a 4m partial 4m bit 00000h to 3ffffh 8m partial 8m bit 00000h to 7ffffh 8m partial 8m bit 00000h to 7ffffh 16m partial 16m bit 00000h to fffffh
132 psram type 7 psram_type07_13_a1 november 2, 2004 advance information power down program sequence the program requires 6 read/write operations with a unique address. between each read/write operation requires that device be in standby mode. the following table shows the detail sequence. the first cycle reads from the most significant address (msb). the second and third cycle are to write ba ck the data (rda) read by first cycle. if the second or third cycle is written in to the different address, the program is cancelled, and the data wri tten by the second or third cycle is valid as a normal write operation. the fourth and fifth cycles write to msb. the data from the fourth and fifth cycles is ?don?t care.? if the fourth or fifth cycles are written into different address, the program is also cancelled but write data might not be written as normal write operation. the last cycle is to read from specific address key for mode selection. once this program sequence is performed from a partial mode to the other partial mode, the written data stored in memory ce ll array can be lost. so, it should per - form this program prior to regular read/w rite operation if partial mode is used. address key the address key has following format. cycle # operation address data 1st read 3fffffh (msb) read data (rda) 2nd write 3fffffh rda 3rd write 3fffffh rda 4th write 3fffffh don?t care (x) 5th write 3fffffh x 6th read address key read data (rdb) mode address 32m 64m a21 a20 a19 a18 - a0 binary sleep (default) sleep (default) 1 1 1 1 3fffffh 4m partial n/a 1 1 0 1 37ffffh 8m partial 8m partial 1 0 1 1 2fffffh n/a 16m partial 1 0 0 1 27ffffh
november 2, 2004 psram_type07_13_a1 psram type 7 133 advance information absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditi ons (see warning below) notes: 1. maximum dc voltage on input and i/o pins is v dd +0.2v. during voltage transitions, inputs can positive overshoot to v dd +1.0v for periods of up to 5 ns. 2. minimum dc voltage on input or i/o pins is -0.3v. during voltage transitions, inputs can negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operating ranges for th e semiconductor device. all the de- vice?s electrical characteristics are warr anted when operated within these ranges. always use semiconductor devices within the recommended operating conditions . operation outside these ranges can adversely affect reliability and could result in device failure. no warranty is made with respect to us es, operating conditions, or combinatio ns not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fu jitsu representative before- hand. package capacitance test conditions: t a = 25c, f = 1.0 mhz item symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage at any pin relative to v ss v in , v out -0.5 to +3.6 v short circuit output current i out 50 ma storage temperature t stg -55 to +125 c parameter symbol min max unit supply voltage v dd 2.7 3.1 v v ss 0 0 v high level input voltage (note 1) v ih v dd 0.8 v dd +0.2 v high level input voltage (note 1) v il -0.3 v dd 0.2 v ambient temperature t a -30 85 c symbol description te s t s e t u p ty p max unit c in1 address input capacitance v in = 0v ? 5 pf c in2 control input capacitance v in = 0v ? 5 pf c io data input/output capacitance v io = 0v ? 8 pf
134 psram type 7 psram_type07_13_a1 november 2, 2004 advance information dc characteristics (under recommended conditions unless otherwise noted) notes: 1. all voltages are referenced to v ss . 2. dc characteristics are measured after following power-up timing. 3. i out depends on the output load conditions. parameter symbol test conditions 16m 32m 64m unit min. max. min. max. min. max. input leakage current i li v in = v ss to v dd -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output leakage current i lo v out = v ss to v dd , output disable -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 a output high voltage level v oh v dd = v dd (min), i oh = ?0.5ma 2.2 ? 2.4 ? 2.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 ? 0.4 ? 0.4 v v dd power down current i ddps v dd = v dd max., v in = v ih or v il , ce2 0.2 v sleep 10 ? 10 ? 10 a i ddp4 4m partial n/a ? 40 n/a a i ddp8 8m partial n/a ? 50 ? 80 a i ddp16 16m partial n/a n/a ? 100 a v dd standby current i dds v dd = v dd max., v in = v ih or v il ce 1 = ce2 = v ih ? 1 ? 1.5 ? 1.5 ma i dds1 v dd = v dd max., v in 0.2v or v in v dd ? 0.2v, ce 1 = ce2 v dd ? 0.2v ta< + 85 c ? 100 ? 80 ? 170 a ta< + 40 c 90 a v dd active current i dda1 v dd = v dd max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma t rc / t wc = min. ? 20 ? 30 ? 40 ma i dda2 t rc / t wc = 1 s ? 3 ? 3 ? 5 ma v dd page read current i dda3 v dd = v dd max., v in = v ih or v il , ce 1 = v il and ce2= v ih , i out =0ma, t prc = min. n/a ? 10 ? 10 ma
november 2, 2004 psram_type07_13_a1 psram type 7 135 advance information ac characteristics (under recommended operating condit ions unless otherwise noted) read operation notes: 1. maximum value is applicable if ce#1 is kept at low without change of address input of a3 to a21. if needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. address should not be changed within minimum t rc . 3. the output load 50 pf wi th 50 ohm termination to v dd x 0.5 (16m), the output load 50 pf (32m and 64m). 4. the output load 5pf. 5. applicable to a3 to a21 (32m an d 64m) when ce1# is kept at low. 6. applicable only to a0, a1 and a2 (32m and 64m) when ce1# is kept at low fo r the page address access. 7. in case page read cycle is continued with keeping ce1# stay s low, ce1# must be brought to high within 4 s. in other words, page read cycle must be closed within 4 s. 8. applicable when at least two of address inputs among applicable are switched from previous state. 9. t rc (min) and t prc (min) must be satisfied. 10. if actual value of t whol is shorter than specified minimum values, the actual t aa of following read can become longer by the amount of subtracting the actual value from the specified minimum value. parameter symbol 16m 32m 64m unit notes min. max. min. max. min. max. read cycle time t rc 70 1000 65 1000 65 1000 ns 1, 2 ce1# access time t ce ?60?65?65ns 3 oe# access time t oe ?40?40?40ns 3 address access time t aa ?60?65?65ns 3, 5 lb# / ub# access time t ba ?30?30?30ns 3 page address access time t paa n/a ? 20 ? 20 ns 3,6 page read cycle time t prc n/a 20 1000 20 1000 ns 1, 6, 7 output data hold time t oh 5?5?5?ns 3 ce1# low to output low-z t clz 5?5?5?ns 4 oe# low to output low-z t olz 0?0?0?ns 4 lb# / ub# low to output low-z t blz 0?0?0?ns 4 ce1# high to output high-z t chz ?20?20?20ns 3 oe# high to output high-z t ohz ?20?14?14ns 3 lb# / ub# high to output high-z t bhz ?20?20?20ns 3 address setup time to ce1# low t asc ? 6??6??6?ns address setup time to oe# low t aso 10 ? 10 ? 10 ? ns address invalid time t ax ?10?10?10ns 5, 8 address hold time from ce1# high t chah -6 ? ?6 ? ?6 ? ns 9 address hold time from oe# high t ohah -6 ? ?6 ? ?6 ? ns we# high to oe# low time for read t whol 10 1000 12 ? 25 ? ns 10 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns
136 psram type 7 psram_type07_13_a1 november 2, 2004 advance information ac characteristics write operation notes: 1. maximum value is applicable if ce1# is kept at low without any address change. if the relaxation is needed by system operation, please contact local spansion representative for the relaxation of 1s limitation. 2. minimum value must be equal or gr eater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wr ). 3. write pulse is defined from high to low transition of ce1#, we#, or lb#/ub#, whichever occurs last. 4. applicable for byte mask only. byte mask setup time is defined to the high to low transition of ce1# or we# whichever occurs last. 5. applicable for byte mask only. byte mask hold time is defi ned from the low to high transi tion of ce1# or we# whichever occurs first. 6. write recovery is defined from low to high transition of ce1#, we#, or lb#/ub#, whichever occurs first. 7. t wph minimum is absolute minimum value for device to de tect high level. and it is defined at minimum v ih level. 8. if oe# is low after minimum t ohcl , read cycle is initiated. in other words, oe # must be brought to high within 5ns after ce1# is brought to low. once read cycle is initia ted, new write pulse should be input after minimum t rc is met. 9. if oe# is low after new address input, read cycle is initiated. in other word, oe# must be brought to high at the same time or before new address valid. once read cycle is init iated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol 16m 32m 64m unit notes min. max. min. max. min. max. write cycle time t wc 70 1000 65 1000 65 1000 ns 1,2 address setup time t as 0 ? 0 ? 0 ? ns 3 ce1# write pulse width t cw 45 ? 40 ? 40 ? ns 3 we# write pulse width t wp 45 ? 40 ? 40 ? ns 3 lb#/ub# write pulse width t bw 45 ? 40 ? 40 ? ns 3 lb#/ub# byte mask setup time t bs -5 ? ?5 ? ?5 ? ns 4 lb#/ub# byte mask hold time t bh -5 ? ?5 ? ?5 ? ns 5 write recovery time t wr 0 ? 0 ? 0 ? ns 6 ce1# high pulse width t cp 10 ? 12 ? 12 ? ns we# high pulse width t whp 7.5 1000 7.5 1000 7.5 1000 ns 7 lb#/ub# high pulse width t bhp 10 1000 12 1000 12 1000 ns data setup time t ds 15 ? 12 ? 12 ? ns data hold time t dh 0 ? 0 ? 0 ? ns oe# high to ce1# low setup time for write t ohcl -5 ? ?5 ? ?5 ? ns 8 oe# high to address setup time for write t oes 0 ? 0 ? 0 ? ns 9 lb# and ub# write pulse overlap t bwo 30 ? 30 ? 30 ? ns
november 2, 2004 psram_type07_13_a1 psram type 7 137 advance information ac characteristics power down parameters notes: 1. applicable also to power-up. 2. applicable when 4mb and 8mb partial modes are programmed. other timing parameters notes: 1. some data might be written into any address location if t chwx (min) is not satisfied. 2. the input transition time (t t ) at ac testing is 5ns as shown in below. if actu al tt is longer than 5ns, it can violate the ac specification of some of the timing parameters. parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce2 low setup time for power down entry t csp 10 ? 10 ? 10 ? ns ce2 low hold time after power down entry t c2lp 80 ? 65 ? 65 ? ns ce1# high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? 300 ? 300 ? s 1 ce1# high hold time following ce2 high after power down exit [not in sleep mode] t chhp n/a 1 ? 1 ? s 2 ce1# high setup time following ce2 high after power down exit t chs 0 ? 0 ? 0 ? ns 1 parameter symbol 16m 32m 64m unit note min. max. min. max. min. max. ce1# high to oe# invalid time for standby entry t chox 10 ? 10 ? 10 ? ns ce1# high to we# invalid time for standby entry t chwx 10 ? 10 ? 10 ? ns 1 ce2 low hold time after power-up t c2lh 50 ? 50 ? 50 ? s ce1# high hold time following ce2 high after power-up t chh 300 ? 300 ? 300 ? s input transition time t t 1 25 1 25 1 25 ns 2
138 psram type 7 psram_type07_13_a1 november 2, 2004 advance information ac characteristics ac test conditions ac measurement output load circuits figure 53. ac output load circuit ? 16 mb figure 54. ac output load circuit ? 32 mb and 64 mb symbol description te s t s e t u p value unit note v ih input high level v dd * 0.8 v v il input low level v dd * 0.2 v v ref input timing measurement level v dd * 0.5 v t t input transition time between v il and v ih 5 ns device under test v dd v dd *0.5 v v ss out 0.1 f 50 pf 50 ohm device under test v dd v ss out 0.1 f 50pf
november 2, 2004 psram_type07_13_a1 psram type 7 139 advance information timing diagrams read timings note: this timing diagram assumes ce2=h and we#=h. figure 55. read timing #1 (basic timing) note: this timing diagram assumes ce2=h and we#=h. figure 56. read timing #2 (oe# address access t ce valid data output address ce1# dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb#/ ub# t oe t ba t blz t clz t aa valid data output address ce 1# dq (output) t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso lb#/ub#
140 psram type 7 psram_type07_13_a1 november 2, 2004 advance information note: this timing diagram assumes ce2=h and we#=h. figure 57. read timing #3 (lb#/ub# byte access) note: this timing diagram assumes ce2=h and we#=h. figure 58. read timing #4 (page address access after ce1# control access for 32m and 64m only) t aa valid data output address dq1-8 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq9-16 (output) t blz t ba t blz t oh t bhz t oh valid data output ce1#, oe# valid data output (normal access) a ddress (a2-a0) ce1# dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa a ddress (a21-a3) address valid t paa t oh t prc t paa t prc t oh address valid address valid t rc t asc lb#/ub#
november 2, 2004 psram_type07_13_a1 psram type 7 141 advance information notes: 1. this timing diagram assumes ce2=h and we#=h. 2. either or both lb# and ub# must be low when both ce1# and oe# are low. figure 59. read timing #5 (random and page address access for 32m and 64m only) write timings note: this timing diagram assumes ce2=h. figure 60. write timing #1 (basic timing) valid data output (normal access) a ddress (a2-a0) ce 1# dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa a ddress (a21-a3) address valid t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso lb#/ub# t as valid data input a ddress ce1# dq (input) we# t dh t ds t wc t wr t wp t cw lb#, ub# t as t bw address valid t as t as t wr oe# t ohcl t as t as t wr t cp t whp t bhp
142 psram type 7 psram_type07_13_a1 november 2, 2004 advance information note: this timing diagram assumes ce2=h. figure 61. write timing #2 (we# control) note: this timing diagram assumes ce2=h and oe#=h. figure 62. write timing #3-1 (we#/lb# /ub# byte write control) t as a ddress we# ce1# t wc t wr t wp lb#, ub# address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah t whp t as a ddress we# ce1# t wc t wr t wp lb# address valid t as t wr t wp valid data input dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp
november 2, 2004 psram_type07_13_a1 psram type 7 143 advance information note: this timing diagram assumes ce2=h and oe#=h. figure 63. write timing #3-3 (we#/lb# /ub# byte write control) note: this timing diagram assumes ce2=h and oe#=h. figure 64. write timing #3-4 (we#/lb# /ub# byte write control) t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw valid data input dq1-8 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq9-16 (input) t bs t bh t bs t bh t whp t as a ddress we# ce1# t wc t wr t bw lb# address valid t as t wr t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t wr t bw t as t wr t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo t bhp t bhp
144 psram type 7 psram_type07_13_a1 november 2, 2004 advance information read/write timings notes: 1. this timing diagram assumes ce2=h. 2. write address is valid from either ce1# or we# of last falling edge. figure 65. read/write timing #1-1 (ce1# control) notes: 1. this timing diagram assumes ce2=h. 2. oe# can be fixed low during write operation if it is ce1# controlled write at read-write-read sequence. figure 66. read / write timing #1-2 (ce1#/we#/oe# control) read data output a ddress ce1# dq we# t wc t cw oe# t ohcl ub#, lb# t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t clz t oh read data output a ddress ce1# dq we# t wc t wp oe# t ohcl ub#, lb# t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
november 2, 2004 psram_type07_13_a1 psram type 7 145 advance information notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 67. read / write timing #2 (oe#, we# control) notes: 1. this timing diagram assumes ce2=h. 2. ce1# can be tied to low for we# and oe# controlled operation. figure 68. read / write timing #3 (oe#, we#, lb#, ub# control) read data output a ddress ce1# dq we# t wc t wp oe# ub#, lb# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah t whol read data output a ddress ce1# dq we# t wc t bw oe# ub#, lb# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oes t whol t wr
146 psram type 7 psram_type07_13_a1 november 2, 2004 advance information note: the t c2lh specifies after v dd reaches specified minimum level. figure 69. power-up timing #1 note: the t chh specifies after v dd reaches specified minimum level and applicable to both ce1# and ce2. figure 70. power-up timing #2 note: this power down mode can be also used as a reset timi ng if power-up timing abov e could not be satisfied and power-down program was not performed prior to this reset. figure 71. power down entry and exit timing t c2lh ce1# v dd v dd min 0v ce2 t chh t chs ce1# v dd v dd min 0v ce2 t chh t csp ce1# power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z
november 2, 2004 psram_type07_13_a1 psram type 7 147 advance information note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce1# low to high transition. figure 72. standby entry timing after read or write notes: 1. the all address inputs must be high from cycle #1 to #5. 2. the address key must confirm the format specified in page 132. if not, the operation and data are not guaranteed. 3. after t cp following cycle #6, the power down program is completed and returned to the normal operation. figure 73. power down program timing (for 32m/64m only) t chox ce1# oe# we# active (read) standby active (write) standby t chwx address ce1# dq* 3 we# t rc oe# lb#, ub# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp t cp * 3 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb
148 revision summary s71pl129jxx_00_a5_e december 23, 2004 advance information revision summary revision a0 (june 9, 2004) initial release. revision a1 (july 19, 2004) global change change all instances of fasl to spansion added colophon text. ?product selector guide? on page 2 replaced ? s71pl129ja0-9z? with ?s71pl129ja0-9p?. ?ordering information? on page 9 in model number section replaced psram part number with ?see valid combinations table?. revision a2 (july 21, 2004) ?connection diagram? on page 7 changed row d of pinout for accuracy. added the following note: ?may be shared depend ing on density:a21 is shared for the 64m psram configuration;a20 is shred for the 32m psram co nfiguration; a19 is shared for the 16m psram configuration. revision a3 (october 18, 2004) core flash module replaced core flash module from s29pl127j_064j_032j_mcp_00_a1_e to s29pl129j_mcp_00_a0 revision a4 (november 30, 2004) product selector guide added a new model number. valid combinations table whole table updated with new opns. revision a5 (december 23, 2004) connection diagram updated pin l5. valid combinations table added a note to the bottom of the table.
december 23, 2004 s71pl129jxx_00_a5_e revision summary 149 advance information colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is se cured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear re action control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note th at spansion llc will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex - port under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without noti ce. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assu mes no liability for any damages of any kind arising out of the use of the informatio n in this document. copyright ?2004 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion llc. o ther company and product names used in this publication are for identification purpose s only and may be trademarks of their respective companies.

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